专利内容由知识产权出版社提供
专利名称：FORMING A COMPACT MULTILEVEL
INTERCONNECTION METALLURGY SYSTEMFOR SEMI-CONDUCTOR DEVICES
发明人：CASS E,US,ENICHEN W,US,HAVAS J,US申请号：US30157072申请日：19721027公开号：US3844831A公开日：19741029
摘要：In this method, the multi-level interconnection metallurgy system is made morecompact by eliminating the need for pads normally associated with via connectionsbetween the metallurgy layers. The method consists of forming a first dielectric layer ona semiconductor substrate, forming the first interconnection metallurgy level on the firstlayer, depositing a second dielectric layer over the metallurgy layer wherein the seconddielectric layer is a material different from the material of the first dielectric layer,forming via holes in the second dielectric layer of a diameter substantially equal to orlarger than the width of the underlying interconnection lines of the first metallurgypattern, and forming a second interconnection metallurgy system over the seconddielectric layer with the conductive lines of the second metallurgy layer having a uniformwidth over the via holes.
申请人：IBM,US
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