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专利名称：Low power voltage multiplier circuit发明人：Joseph W. Harmon,James H. Atherton申请号：US06/174928申请日：19800804公开号：US04344003A公开日：19820810
摘要：A voltage multiplier includes an inverter connected at its output to one plate ofa capacitor for applying a first or a second voltage thereto, a first transistor switch which,when on, applies a second voltage to the second plate of the capacitor, and a secondtransistor switch which, when on, couples the second side of the capacitor to a load. Forone polarity of input signal the inverter output switches from the first to the secondvoltage to produce an enhanced voltage at the second plate which is coupled via thesecond switch to the load. For the opposite polarity of input signal the inverter outputswitches from the second to the first voltage and the first switch is turned on. The inputsignal to the inverter is delayed and circuits responsive to the input signals are coupledto the first and second switches for:
(a) in response to signals of the one polarity turning off the first switch prior to theproduction of the enhanced voltage and the turn on of the second switch; and
< P>(b) in response to signals of opposite polarity turning off the second switch priorto the turn on of the first switch and the switching of the inverter output from the secondto the first voltage.
申请人：RCA CORPORATION
代理人：Samuel Cohen,Henry I. Schanzer
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