ht82a836rv110

·ApplicationNote-HA0075EMCUResetandOscillatorCircuitsApplicationNoteFeatures

·USB2.0fullspeedcompatible

·USBspecV1.1fullspeedoperationandUSBaudio

·352´8DataMemoryintwobanks·Programmablefrequencydividerfunction·IntegratedSPIhardwareinterface

·PortAwake-uponrisingorfallingtransitions·6-channel12-bitA/Dconverter·2-channelPWMfunction·mLawCompander

·Power-downfunctionandwake-upreducepower

deviceclassspecV1.0

·OperatingvoltageatfSYS=6M/12MHz:3.3V~5.5V·Lowvoltageresetfunction

·Embeddedhigh-performance16-bitPCMADC·IntegratedDigitalPGA-ProgrammableGainAmpli-

fier

·48kHz/8kHzsamplingrateforaudioplaybackse-

lectedbysoftware

·8kHz/16kHzaudiorecordingsamplingrateselected

consumption

·Uptoof44bidirectionalI/Olines

·Dual16-bitprogrammableTimer/EventCounters

bysoftware

·EmbeddedclassABpoweramplifierforspeakerdriv-

withoverflowinterrupts

·WatchdogTimer

·16-levelsubroutinenesting·Bitmanipulationinstruction·15-bittablereadinstruction·63powerfulinstructions

·Allinstructionsexecutedwithinoneortwomachine

ing

·EmbeddedHighPerformance16-bitaudioDAC·Audioplaybackdigitalvolumecontrol·5endpointssupportedincludingendpoint0·Supports1Control,2Interruptsand2Isochronous

transfers

·TwohardwareimplementedIsochronoustransfers·TotalFIFOsize:496bytes-8,8,384,,32for

cycles

·Lowvoltageresetfunction(3.0V±0.3V)·80-pinLQFP(10mm´10mm)packagetype

EP0~EP4

·8192´16ProgramMemory

GeneralDescription

TheHT82A836Risan8-bithigh-performanceRISCmicrocontrollerdesignedforUSBphoneproductappli-cations.ToensureahighleveloffunctionalintegrationforUSBphoneapplications,this8-bitmicrocontrollerin-cludesimportantfeaturessuchas16-bitPCMA/DCon-verter,USBtransceiver,SerialInterfaceEngine,audioclassprocessingunit,mlawCompander,6-channel12-bitADC,2-channelPWMandFIFO.

TheDACintheHT82A836Roperatesatasamplingrateof48kHz/8kHzandthe16-bitPCMADCoperatesatfrequencyof8kHz/16kHzfortheMicrophoneinput,withtheoptionsselectedusingsoftware.TheintegratedDACalsoincludesadigitallyprogrammablegainampli-fierwitharangeof-32dBto+6dB.ThedigitalgainrangeoftheADCinputisfrom0dBto19.5dB.

Rev.1.101August5,2011

HT82A836RBlockDiagramPinAssignmentRev.1.102August5,2011

HT82A836RPinDescription

PinNameROUTLOUTAVSS4AVSS3AVSS2AVSS1BIASMUSIC_INAVDD4AVDD3AVDD2AVDD1AN0~AN5VAGRefVAGTI+TI-TGI/OOO¾¾¾¾¾I¾¾¾¾IIOIIO¾¾¾¾¾¾¾¾¾¾¾¾¾¾¾ConfigurationOption¾¾¾RightdriveranalogoutputLeftdriveranalogoutput12-bitADCnegativepowersupply,groundPCMADCnegativepowersupply,groundAudiopoweramplifiernegativepowersupply,groundAudioDACnegativepowersupply,groundAcapacitorshouldbeconnectedtogroundtoincreasehalf-supplystabilityPoweramplifierinputsignalsourceifregisterbitSELW=²1².TheanalogsignalinputwillamplifybythepowerampthenoutputtoROUTandLOUTatthesametime.12-bitADCpositivepowersupplyPCMADCpositivepowersupplyAudiopoweramplifierpositivepowersupplyAudioDACpositivepowersupply12-bitADCanaloginputsPCMADCanaloggroundreferencevoltage(shouldleftopenorconnectedbyabypasscapacitor(Ex:100pF)toground)PCMADCanaloggroundvoltage(shouldconnectedbyabypasscapacitor(Ex:10mF)toground)OPAMPnon-invertinginputOPAMPinvertinginputOPAMPgainsettingoutputPWMoutputsDescriptionPWM0~PWM1OPA0~PA7Bidirectional8-bitinput/outputport.Eachbitcanbeconfiguredasawake-upPull-highinputbyaconfigurationoption.SoftwareinstructionsdetermineifthepinisaWake-upI/OCMOSoutputorSchmitttriggerinput.ConfigurationoptionsdeterminewhichNMOS/CMOSpinsonthisporthavepull-highresistors.TheoutputstructurecanbeeitherOutputNMOSorCMOStypesdeterminedviaconfigurationoption.I/OPull-highWake-upBidirectional8-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmitttriggerinput.Configurationoptionsdeterminewhichpinsonthisporthavepull-highresistors.Bidirectional8-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmitttriggerinput.Configurationoptionsdeterminewhichpinsonthisporthavepull-highresistors.PinPC0issharedwiththebuzzerpinBZ.PinsPC1/PC2aresharedwithtimerinputpinsTMR0/TMR1.PinsPC4/PC5aresharedwithSerialInterfacepinsSDO/SDI.PinPC6issharedwiththeSerialInterfaceSlaveSelectpin.PinPC7issharedwiththeSerialInterfaceclocksignal.Bidirectional8-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmitttriggerinput.Configurationoptionsdeterminewhichpinsonthisporthavepull-highresistors.PB0~PB7PC0/BZPC1/TMR0PC2/TMR1PC3PC4/SDOPC5/SDIPC6/SCSPC7/SCKPD0~PD7I/OPull-highWake-upI/OPull-highWake-upRev.1.103August5,2011

HT82A836RPinNameI/OConfigurationOptionPull-highWake-upDescriptionBidirectional8-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmitttriggerinput.Configurationoptionsdeterminewhichpinsonthisporthavepull-highresistors.PE7issharedwithexternalinterruptinputINT.Bidirectional4-bitinput/outputport.SoftwareinstructionsdetermineifthepinisaCMOSoutputorSchmitttriggerinput.Configurationoptionsdeterminewhichpinsonthisporthavepull-highresistors.PositivedigitalpowersupplyNegativedigital&I/Opowersupply,groundPositivedigitalpowersupplyNegativedigitalpowersupply,groundOSCI,OSCOareconnectedtoan6MHzor12MHzcrystal/resonator,determinedbysoftwareinstructions,fortheinternalsystemclock.Schmitttriggerresetinput,activelowUSBD-lineUSBD+line3.3VregulatoroutputPE0~PE6PE7/INTI/OPF0~PF3DVDD2DVSS2DVDD1DVSS1OSCIOSCORESETUSBDNUSBDPV33OI/O¾¾¾¾IOII/OI/OOPull-highWake-up¾¾¾¾¾¾¾¾¾AbsoluteMaximumRatings

SupplyVoltage...........................VSS-0.3VtoVSS+6.0VInputVoltage..............................VSS-0.3VtoVDD+0.3VIOLTotal..............................................................150mATotalPowerDissipation.....................................500mW

StorageTemperature............................-50°Cto125°COperatingTemperature...........................-40°Cto85°CIOHTotal............................................................-100mA

Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder²AbsoluteMaximumRatings²may

causesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

D.C.Characteristics

SymbolVDDIDD1IDD2ParameterOperatingVoltageOperatingCurrentOperatingCurrentTestConditionsVDD¾5V5VConditions¾Noload,fSYS=12MHzADCon,DAConNoload,fSYS=12MHzADCoff,DACoffNoload,systemHALT,USBtransceiverand3.3Vregulatoron¾¾¾¾VOL=0.1VDDMin.3.3¾¾¾00.7VDD00.8VDD¾Typ.5.0128330¾¾¾¾5Max.5.5¾¾¾0.3VDDVDD0.4VDDVDD¾Ta=25°CUnitVmAmAISUSVIL1VIH1VIL2VIH2IOLSuspendCurrentInputLowVoltageforI/OPortsInputHighVoltageforI/OPortsInputLowVoltage(RESET)InputHighVoltage(RESET)I/OPortSinkCurrent5V¾¾¾¾5VmAVVVVmARev.1.104August5,2011

HT82A836RSymbolIOHRPHVLVR0VV33OParameterI/OPortSourceCurrentPull-highResistanceLowVoltageReset3.3VRegulatorOutputTestConditionsVDD5V5V5V5VConditionsVOH=0.9VDD¾¾IV33O=-5mAMin.¾302.73.0Typ.-5403.03.3Max.¾803.33.6UnitmAkWVVDAC+PowerAmp:TestCondition:Measurementbandwidth20Hzto20kHz,fS=48kHz.Lineoutputseriescapacitorwith220mF.THD+NTHD+N(Note)5V4Wload8Wload4Wload8Wload4Wload8Wload4Wload,THD=10%8Wload,THD=10%¾¾¾¾¾¾¾¾-30-3581828788400200¾¾¾¾¾¾¾¾dBdBdBdBdBdBmW/chmW/chSNRDASignaltoNoiseRatioNote15VDRDynamicRange5VPOUTOutputPower5VPCMADC:SNRADVAGVPEAKSignaltoNoiseRatioReferenceVoltage5V5V¾¾¾¾¾¾772.01.575¾¾¾dBVVPKPeakSingleFrequencyTone5VAmplitudewithoutClippingNote:Sinewaveinputat1kHz,-6dB

A.C.Characteristics

SymbolfSYSParameterSystemClock(CrystalOSC)TestConditionsVDD5V5V¾¾¾¾¾Conditions¾¾¾¾¾¾¾Min.0.4¾1¾1¾¾Typ.¾100¾1024¾8032Max.12¾¾¾¾¾¾Ta=25°CUnitMHzmsms*tSYSmstADtADtWDTOSCWatchdogOscillatorPeriodtREStSSTtINTtADCtADCSResetLowPulseWidthSystemStart-upTimerPeriodInterruptPulseWidthA/DConversionTimeA/DSamplingTimeNote:*tSYS=1/fSYS

Rev.1.105August5,2011

HT82A836RSystemArchitecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheinter-nalsystemarchitecture.Therangeofdevicestakead-vantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyalloperationsoftheinstructionset.Itcar-riesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.Theinter-naldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitecturalfea-turesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/Ocontrolsystemwithmaximumreliabilityandflexibility.ClockingandPipelining

Themainsystemclock,derivedfromaCrystal/Resona-torissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecution

functions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncy-cles,thepipeliningstructureofthemicrocontrolleren-suresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesarerequiredtocom-pleteinstructionexecution.Anextracycleisrequiredastheprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.ProgramCounter

Duringprogramexecution,theProgramCounterisusedtokeeptrackoftheaddressofthenextinstructiontobeexecuted.Itisautomaticallyincrementedbyoneeachtimeaninstructionisexecutedexceptforinstructions,suchas²JMP²or²CALL²,thatdemandajumptoanon-consecutiveProgramMemoryaddress.NotethattheProgramCounterwidthvarieswiththeProgramMemorycapacitydependinguponwhichdeviceisse-lected.

SystemClockingandPipelining

InstructionFetching

Rev.1.106August5,2011

HT82A836RHowever,itmustbenotedthatonlythelower8bits,knownastheProgramCounterLowRegister,aredi-rectlyaddressablebyuser.

Whenexecutinginstructionsrequiringjumpstonon-consecutiveaddressessuchasajumpinstruction,asubroutinecall,interruptorreset,etc.,themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forcondi-tionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdis-cardedandadummycycletakesitsplacewhilethecor-rectinstructionisobtained.

ThelowerbyteoftheProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwritableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythislowbyteisavailableformanipulation,thejumpsarelimitedtothepresentpageofmemory,thatis256locations.Whensuchprogramjumpsareexecuteditshouldalsobenotedthatadummycyclewillbein-serted.

ThelowerbyteoftheProgramCounterisfullyaccessi-bleunderprogramcontrol.ManipulatingthePCLmightcauseprogrambranching,soanextracycleisneededtopre-fetch.FurtherinformationonthePCLregistercanbefoundintheSpecialFunctionRegistersection.

Stack

ThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackhas16levelsandisneitherpartofthedatanorpartoftheprogramspace,andcanneitherbereadfromnorwrittento.TheactivatedlevelisindexedbytheStackPointer,SP,whichcanalsoneitherbereadfromnorwrittento.Atasubroutinecallorinterruptacknowl-edgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheac-knowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowal-lowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutinein-structioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcases,whichmightcauseunpredictableprogrambranching.

ModeInitialResetUSBInterruptTimer/EventCounter0OverflowTimer/EventCounter1OverflowPlayInterruptMultiFunctionInterruptRecordInterruptSkipLoadingPCLJump,CallBranchReturnfromSubroutineProgramCounterBitsb120000000b110000000b100000000b90000000b80000000b70000000b60000000b50000000b40000111b30011001b20101010b10000000b00000000ProgramCounter+2PC12PC11PC10PC9#12S12#11S11#10S10#9S9PC8#8S8@7#7S7@6#6S6@5#5S5@4#4S4@3#3S3@2#2S2@1#1S1@0#0S0ProgramCounter

Note:

PC12~PC8:CurrentProgramCounterbits@7~@0:PCLbits

#12~#0:InstructioncodeaddressbitsS12~S0:Stackregisterbits

Rev.1.107August5,2011

HT82A836RSpecialVectors

WithintheProgramMemory,certainlocationsarere-servedforspecialusagesuchasresetandinterrupts.

·Location000H

Thisvectorisreservedforusebythedeviceresetforprograminitialisation.Afteradeviceresetisinitiated,theprogramwilljumptothislocationandbeginexecution.

·Location004H

ArithmeticandLogicUnit-ALU

Thearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicop-erationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedin-structioncodesandperformstherequiredarithmeticorlogicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroper-ationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyup-datedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

·Arithmeticoperations:ADD,ADDM,ADC,ADCM,

ThisvectorisusedbytheUSBinterrupt.IfaUSBin-terruptoccurs,theprogramwilljumptothislocationandbeginexecutioniftheUSBinterruptisenabledandthestackisnotfull.

·Location008H

ThisvectorisusedbytheTimer/EventCounter0.Ifacounteroverflowoccurs,theprogramwilljumptothislocationandbeginexecutionifthetimerinterruptisenabledandthestackisnotfull.

·Location00CH

ThisvectorisusedbytheTimer/Eventcounter1.Ifacounteroverflowoccurs,theprogramwilljumptothislocationandbeginexecutionifthetimerinterruptisenabledandthestackisnotfull.

·Location010H

SUB,SUBM,SBC,SBCM,DAA

·Logicoperations:AND,OR,XOR,ANDM,ORM,

XORM,CPL,CPLA

·RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,

Thisvectorisusedbytheplayinterruptservicepro-gram.Ifplaydataoccurs,theprogramwilljumptothislocationandbeginexecutioniftheplayinterruptisen-abledandthestackisnotfull.

·Location014H

RLC

·IncrementandDecrementINCA,INC,DECA,DEC·Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,

SIZA,SDZA,CALL,RET,RETI

ThisvectorisusedbytheMulti-functioninterrupt.Ifaninterruptresultsfromaserialinterfaceinterrupt,anendof12-bitA/Dconversioncycleoranexternalinter-rupt,theprogramwilljumptothislocationandbeginexecutioniftherelevantinterruptisenabledandthestackisnotfull.

·Location018H

ProgramMemory

TheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ThedevicecontainsOne-TimeProgrammable,OTP,memorywhereuserscanprogramtheirapplicationcodeintothedevice.Byusingtheappropriateprogrammingtools,OTPdevicesofferuserstheflexibilitytofreelydeveloptheirapplica-tions,whichmaybeusefulduringdebugorforproductsrequiringfrequentupgradesorprogramchanges.OTPdevicesarealsoapplicableforuseinapplicationsthatrequirelowormediumvolumeproductionruns.Organisation

TheProgramMemoryhasacapacityof8Kby16bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyseparatetablepointerregisters.

ThisareaisusedbytheRecordinterrupt.Ifrecorddataoccurs,theprogramwilljumptothislocationandbeginexecutionifthetimerinterruptisenabledandthestackisnotfull.

ProgramMemoryStructure

Rev.1.108August5,2011

HT82A836RLook-upTable

AnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointersmustfirstbesetupwhichpointtothedataintheProgramMemorywhichistoberead.Inthisdevicetherearetwotablepointers,thelowbytepointer,TBLPandthehighbytepointer,TBHP.However,thehighbytepointer,TBHP,canonlybeusedifitisenabledusingconfigura-tionoptions.UsingbothtablepointersenablesanyareaintheProgramMemorytobeaddressedwhileifonlythelowbytepointer,TBLP,isusedthenonlythepresentpageorlastpagecanbeaddressed.

Iftheconfigurationoptionsdonotenablethehighbytepointer,thenaftersettingupthelowtablepointer,TBLP,thetabledatacanberetrievedfromthecurrentProgramMemorypageorlastProgramMemorypageusingthe²TABRDC[m]²or²TABRDL[m]²instructions,respec-tively.Whentheseinstructionsareexecuted,thelowerordertablebytefromtheProgramMemorywillbetrans-ferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.

Thefollowingdiagramillustratestheaddressing/dataflowofthelook-uptableusingthesingletableaddresspointerTBLP:

Thefollowingdiagramillustratestheaddressing/dataflowofthelook-uptableusingthedualtableaddresspointersTBLPandTBHP:

DualAddressPointerLook-upTable

TableProgramExample

Thefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocon-trollerusingthesingletabledatapointer,TBLP.Thisex-ampleusesrawtabledatalocatedinthelastpagewhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis²1F00H²whichreferstothestartaddressofthelastpagewithinthe8KProgramMemoryofdevice.Thetablepointerissetupheretohaveanini-tialvalueof²06H².ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress²1F06H²or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisrefer-encedtothefirstaddressofthepresentpageifthe²TABRDC[m]²instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe²TABRDL[m]²instructionisexecuted.

BecausetheTBLHregisterisaread-onlyregisterandcannotberestored,careshouldbetakentoensureitsprotectionifboththemainroutineandInterruptServiceRoutineusethetablereadinstructions.Ifusingthetablereadinstructions,theInterruptServiceRoutinesmaychangethevalueofTBLHandsubsequentlycauseer-rorsifusedagainbythemainroutine.Asaruleitisrec-ommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However,insituationswheresimultaneoususecannotbeavoided,theinter-ruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

SingleAddressPointerLook-upTable

Iftheconfigurationoptionsenablethehightablepointer,TBHP,thenthisregistertogetherwiththelowtablepointer,TBLP,canbeusedtogetherasapairtopointtoanylocatedintheProgramMemory.Aftersettingupboththelowandhighbytetablepointers,thetabledatacanthenberetrievedfromanyareaofProgramMemoryusingthe²TABRDC[m]²instructionorfromthelastpageoftheProgramMemoryusingthe²TABRDL[m]²instruction.Wheneitheroftheseinstructionsareexe-cuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.

Rev.1.109August5,2011

HT82A836Rtempreg1tempreg2

dbdb::a,06htblp,a::

tempreg1

??

;temporaryregister#1;temporaryregister#2

movmov

;initialisetablepointer-notethatthisaddress;isreferenced

;tothelastpageorpresentpage

tabrdl

;;;;transfersvalueintablereferencedbytablepointertotempregl

dataatprog.memoryaddress²1F06H²transferredtotempreg1andTBLH

dectabrdl

tblptempreg2

;reducevalueoftablepointerbyone;;;;;;;;

transfersvalueintablereferencedbytablepointertotempreg2

dataatprog.memoryaddress²1F05H²transferredtotempreg2andTBLH

inthisexamplethedata²1AH²istransferredtotempreg1anddata²0FH²toregistertempreg2

thevalue²00H²willbetransferredtothehighbyteregisterTBLH

::

orgdc

1F00h

;setsinitialaddressoflastpage

00Ah,00Bh,00Ch,00Dh,00Eh,00Fh,01Ah,01Bh::

InstructionTABRDC[m]TABRDL[m]TableLocationBitsb121b111b101b9PC91b8PC81b7@7@7b6@6@6b5@5@5b4@4@4b3@3@3b2@2@2b1@1@1b0@0@0PC12PC11PC10TableLocation

Note:

PC12~PC8:CurrentProgramCounterbits

TBHPregisterbit4~bit0whenTBHPoptionisenabled@7~@0:TablePointerTBLPbits

DataMemory

TheDataMemoryisavolatileareaof8-bitwideRAMin-ternalmemoryandisthelocationwheretemporaryin-formationisstored.Dividedintotwosections,thefirstoftheseisanareaofRAMwherespecialfunctionregistersarelocated.Theseregistershavefixedlocationsandarenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodi-rectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

Organisation

TheRAMDataMemoryissubdividedintotwobanks,knownasBank0andBank1,allofwhichareimple-mentedin8-bitwideRAM.TheBank0DataMemoryissubdividedintotwosections,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.ThestartaddressoftheBank0DataMemoryistheaddress00HandthelastDataMemoryaddressisFFH.TheBank1DataMemoryconsistsonlyofGeneralPurposeDataMemory.ThestartaddressoftheBank1DataMemoryistheaddress40HandthelastDataMemoryaddressisFFH.SelectionofwhichBankistobeusedisimplementedusingtheBankPointer.

Rev.1.1010August5,2011

HT82A836RDataMemoryStructure

Note:

MostoftheRAMDataMemorybitscanbedi-rectlymanipulatedusingthe²SET[m].i²and²CLR[m].i²instructionswiththeexceptionofafewdedicatedbits.TheRAMDataMemorycanalsobeaccessedthroughtheMemoryPointerregistersMP0andMP1.

GeneralPurposeDataMemory

Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserpro-gramforbothreadandwriteoperations.Byusingthe²SET[m].i²and²CLR[m].i²instructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.AstheGeneralPurposeDataMemoryexistsintwobanks,Bank0andBank1,itisnecessarytofirstensurethattheBankPointerisproperlysettothecorrectvaluebeforeaccessingtheGeneralPurposeDataMemory.WhentheBankPointerissettothevalue00H,datafromBank0willbeaccessedandwhensettothevalue01HdatafromBank1willbeaccessed.NotethatBank1mustbeaccessedindirectlyusingtheMem-oryPointerMP1andtheIndirectAddressingRegisterIAR1.

SpecialPurposeDataMemory

ThisareaofDataMemory,islocatedinBank0,whereregisters,necessaryforthecorrectoperationofthemicrocontroller,arestored.Mostoftheregisterscanbereadfromandwrittentobutsomeareprotectedandarereadonly,thedetailsofwhicharelocatedundertherele-vantSpecialFunctionRegistersection.Notethatforlo-cationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue²00H².

SpecialPurposeDataMemoryStructure

Rev.1.10

11

August5,2011

HT82A836RSpecialFunctionRegisters

Toensuresuccessfuloperationofthemicrocontroller,certaininternalregistersareimplementedintheDataMemoryarea.Theseregistersensurecorrectoperationofinternalfunctionssuchastimers,interrupts,USBport,etc.,aswellasexternalfunctionssuchasI/Odatacontrol.ThelocationoftheseregisterswithintheDataMemorybeginsattheaddress²00H².AnyunusedDataMemorylocationsbetweenthesespecialfunctionregis-tersandthepointwheretheGeneralPurposeMemorybeginsisreservedandattemptingtoreaddatafromtheselocationswillreturnavalueof²00H².IndirectAddressingRegister-IAR0,IAR1

TheIndirectAddressingRegisters,IAR0andIAR1,al-thoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregis-ters.ThemethodofindirectaddressingforRAMdatamanipulationusestheseIndirectAddressingRegistersandMemoryPointers,incontrasttodirectmemoryad-dressing,wheretheactualmemoryaddressisspeci-fied.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorre-spondingMemoryPointer,MP0orMP1.Actingasadata.section¢data¢adres1db?adres2db?adres3db?adres4db?blockdb?code.sectionat0¢code¢org00hstart:

movmovmovmovclrincsdzjmp

a,04h;setupsizeofblockblock,a

a,offsetadres1;AccumulatorloadedwithfirstRAMaddressmp0,a;setupmemorypointerwithfirstRAMaddressIAR0mp0blockloop

;clearthedataataddressdefinedbyMP0;incrementmemorypointer

;checkiflastmemorylocationhasbeencleared

pair,IAR0andMP0cantogetheronlyaccessdatafromBank0,whiletheIAR1andMP1registerpaircanac-cessdatafrombothBank0andBank1.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof²00H²andwritingtotheregistersindi-rectlywillresultinnooperation.MemoryPointer-MP0,MP1

Foralldevices,twoMemoryPointers,knownasMP0andMP1areprovided.TheseMemoryPointersarephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregisterspro-vidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAd-dressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspeci-fiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0only,whileMP1andIAR1areusedtoaccessdatafrombothBank0andBank1.

ThefollowingexampleshowshowtoclearasectionoffourRAMlocationsalreadydefinedaslocationsadres1toadres4.

loop:

continue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryad-dresses.

Rev.1.1012August5,2011

HT82A836RBankPointer-BP

TheDataMemoryisdividedintotwoBanks,knownasBank0andBank1.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.IfdatainBank0istobeaccessed,thentheBPregistermustbeloadedwiththevalue²00²,whileifdatainBank1istobeac-cessed,thentheBPregistermustbeloadedwiththevalue²01².

UsingMemoryPointerMP0andIndirectAddressingRegisterIAR0willalwaysaccessdatafromBank0,irre-spectiveofthevalueoftheBankPointer.

TheDataMemoryisinitialisedtoBank0afterareset,exceptfortheWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.DirectlyaddressingtheDataMemorywillal-waysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.Accumulator-ACC

TheAccumulatoriscentraltotheoperationofanymicrocontrollerandiscloselyrelatedwithoperationscarriedoutbytheALU.TheAccumulatoristheplacewhereallintermediateresultsfromtheALUarestored.WithouttheAccumulatoritwouldbenecessarytowritetheresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc.,totheDataMemoryresultinginhigherprogrammingandtimingoverheads.DatatransferoperationsusuallyinvolvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother,itisnecessarytodothisbypassingthedatathroughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

ProgramCounterLowRegister-PCL

Toprovideadditionalprogramcontrolfunctions,thelowbyteoftheProgramCounterismadeaccessibletopro-grammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimple-mented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylo-cation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypageareper-mitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-upTableRegisters-TBLP,TBLH,TBHPThesethreespecialfunctionregistersareusedtocon-troloperationofthelook-uptable,whichisstoredintheProgramMemory.TBLPisthetablelowbytepointerandindicatesthelowest8-bitaddresslocationwheretheta-bledataislocated.TBHPisthetablehighbytepointerandindicatesthehighestbitaddresslocationwherethetabledataislocated.TheTBHPhighbytetablepointercanonlybeusedifitsconfigurationoptionisselected.Thetablepointersmustbesetupbeforeanytablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe²INC²or²DEC²instructions,al-lowingforeasytabledatapointingandreading.IftheTBHPconfigurationisenabled,thentheTBLPandTBHPregisterpaircanbeusedtogetherwiththe²TABRDC²instructiontopointdirectlytoanylocationintheprogrammemory.TBLHisthelocationwherethehigherorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Theloweror-dertabledatabyteistransferredtoauserdefinedloca-tion.

WatchdogTimerRegister-WDTS

TheWatchdogfeatureofthemicrocontrollerprovidesanautomaticresetfunctiongivingthemicrocontrollerameansofprotectionagainstspuriousjumpstoincorrectProgramMemoryaddresses.Toimplementthis,atimerisprovidedwithinthemicrocontrollerwhichwillissuearesetcommandwhenitsvalueoverflows.ToprovidevariableWatchdogTimerresettimes,theWatchdogTimerclocksourcecanbedividedbyvariousdivisionra-tios,thevalueofwhichissetusingtheWDTSregister.Bywritingdirectlytothisregister,theappropriatedivi-sionratiofortheWatchdogTimerclocksourcecanbesetup.Notethatonlythelower3bitsareusedtosetdivi-sionratiosbetween1and128.StatusRegister-STATUS

This8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanage-mentflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,opera-BankPointer

Rev.1.1013August5,2011

HT82A836RStatusRegister

tionsrelatedtothestatusregistermaygivedifferentre-sultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe²CLRWDT²or²HALT²in-struction.ThePDFflagisaffectedonlybyexecutingthe²HALT²or²CLRWDT²instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

·Cissetifanoperationresultsinacarryduringanad-

likeaglobalenable/disableandisusedtosetalloftheinterruptenablebitsonoroff.Thisbitisclearedwhenaninterruptroutineisenteredtodisablefurtherinterruptandissetbyexecutingthe²RETI²instruction.Noteinsituationswhereotherinterruptsmayrequireservicingwithinpresentinterruptserviceroutines,theEMIbitcanbemanuallysetbytheprogramafterthepresentinter-ruptserviceroutinehasbeenentered.

Timer/EventCounterRegisters-TMRL/TMRH,TMRC

Thedevicecontainstwo16-bitTimer/EventCounters.EachTimer/EventCounterhasanassociatedregisterpair,knownasTMR0L/TMR0HandTMR1L/TMR1Hwhicharethelocationswherethetimer¢s16-bitvalueislocated.Eachtimeralsohasanassociatedcontrolreg-ister,knownasTMR0CandTMR1Cwhichcontainsthesetupinformationfortheassociatedtimer.Input/OutputPortsandControlRegisters

WithintheareaofSpecialFunctionRegisters,theI/Oregistersandtheirassociatedcontrolregistersplayaprominentrole.AllI/OportshaveadesignatedregistercorrespondinglylabeledasPA,PB,PC,PD,PEandPF.TheselabeledI/Oregistersaremappedtospecificad-dresseswithintheDataMemoryasshownintheDataMemorytable,whichareusedtotransfertheappropri-ateoutputorinputdataonthatport.WitheachI/OportthereisanassociatedcontrolregisterlabeledPAC,PBC,PCC,PDC,PECandPFC,alsomappedtospe-cificaddresseswiththeDataMemory.Thecontrolregis-terspecifieswhichpinsofthatportaresetasinputsandwhicharesetasoutputs.Tosetupapinasaninput,thecorrespondingbitofthecontrolregistermustbesethigh,foranoutputitmustbesetlow.Duringprogramini-tialization,itisimportanttofirstsetupthecontrolregis-terstospecifywhichpinsareoutputsandwhichareinputsbeforereadingdatafromorwritingdatatotheI/Oports.Oneflexiblefeatureoftheseregistersistheabilitytodirectlyprogramsinglebitsusingthe²SET[m].i²and²CLR[m].i²instructions.TheabilitytochangeI/Opinsfromoutputtoinputandviceversabymanipulatingspe-cificbitsoftheI/Ocontrolregistersduringnormalpro-gramoperationisausefulfeatureofthesedevices.14

August5,2011

ditionoperationorifaborrowdoesnottakeplacedur-ingasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

·ACissetifanoperationresultsinacarryoutofthe

lownibblesinaddition,ornoborrowfromthehighnib-bleintothelownibbleinsubtraction;otherwiseACiscleared.

·Zissetiftheresultofanarithmeticorlogicaloperation

iszero;otherwiseZiscleared.

·OVissetifanoperationresultsinacarryintothehigh-

est-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

·PDFisclearedbyasystempower-uporexecutingthe

²CLRWDT²instruction.PDFissetbyexecutingthe²HALT²instruction.

·TOisclearedbyasystempower-uporexecutingthe

²CLRWDT²or²HALT²instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecut-ingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

InterruptControlRegisters-INTC0,INTC1,MFI1CThesethree8-bitregisters,knownastheINTC0,INTC1andMFI1Ccontroltheoperationoftheinterrupts.Bysettingvariousbitswithinthisregisterusingstandardbitmanipulationinstructions,theenable/disablefunctionoftheallinterruptscanbeindependentlycontrolled.Amasterinterruptbitwithinthisregister,theEMIbit,actsRev.1.10

HT82A836RPortAWake-upControlRegister-PA_WAKE_CTRL

Thisregisterisusedtoselecttheedgetypethattriggersthewake-upfunctiononthePortApins.Iftheconfigura-tionoptionsselectsomeorallofthePortApinstohaveawake-upfunctionthenthisregistercanbeusedtose-lecteitherwhethertheactiveedgeisanegativeorposi-tivetransition.OnlyPortAisallowedthisselection.PulseWidthModulatorRegisters-PWM0,PWM1,PWMC

Thedevice2integratedPulseWidthModulators.Eachonehasitsownindependentregister,knownasPWM0andPWM1.The8-bitcontentsofeachoftheseregistersdefinethedutycyclevalueforthemodulationcycleofthecorrespondingpulsewidthmodulator.ThePWMCisthecontrolregisterforthePWMfunctionsandcontrolsthemodeselectionandon/offfunction.

A/DConverterRegisters-ADRL,ADRH,ADCR,ACSR

Thedevicecontainsasingle6-channel12-bitA/Dcon-verter.ThecorrectoperationoftheA/Drequirestheuseoftwodataregisters,acontrolregisterandaclocksourceregister.Therearetwodataregisters,ahighbytedataregisterknownasADRH,andalowbytedataregisterknownasADRL.Thesearetheregisterloca-tionswherethedigitalvalueisplacedafterthecomple-tionofananalogtodigitalconversioncycle.ThechannelselectionandconfigurationoftheA/DconverterissetupviathecontrolregisterADCRwhiletheA/Dclockfrequencyisdefinedbytheclocksourceregister,ACSR.USBRegisters

ThedevicecontainsaninternalUSBportwhichiscon-trolledviaseveralregisters.TheseareusedtosetuptheUSBoperation,theexternalpins,errorhandlingetc.AsthisregisterlististoonumeroustolistheredetailscanbefoundintherelevantUSBdescription.PFDRegisters-PFDC,PFDD

ThedevicecontainsafullyintegratedProgrammableFrequencyDriverotherwiseknownasthePFD.TworegisterscontroltheoveralloperationofthePFDtode-terminetheoutputfrequencyandthefunctionen-able/disable.OtherRegisters

Thedevicecontainsseveralotherspecialfunctionreg-istersforcontrolofvariousinternalfunctions.Astheirfunctionaldescriptionistoodetailedtobedescribedheretheirdetailswillbeprovidedintherelevantfunc-tionaldescriptionsection.

Input/OutputPorts

HoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofev-erypinfullyunderuserprogramcontrol,pull-highop-tionsforallportsandwake-upoptionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.Themicrocontrollerprovidesamaximumof44bidirectionalinput/outputlineslabeledwithportnamesPA,PB,PC,PD,PEandPF.TheseI/OportsaremappedtotheDataMemorywithaddressesasshownintheSpecialPurposeDataMemorytable.SevenoftheseI/Olinescanbeusedforinputandoutputopera-tionsandonelineasaninputonly.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction²MOVA,[m]²,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsun-changeduntiltheoutputlatchisrewritten.Pull-highResistors

Manyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexter-nalresistor.Toeliminatetheneedfortheseexternalre-sistors,allI/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectableviaconfigurationoptionsandareimplementedusingaweakPMOStransistor.PortAWake-up

IftheHALTinstructionisexecuted,thedevicewillenterthePowerDownMode,wherethesystemclockwillstopresultinginpowerbeingconserved,afeaturethatisim-portantforbatteryandotherlow-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichisalogicaltransitionononeofthePortA~PortFpinsfromhightolow.AfteraHALTinstructionforcesthemicrocontrollerintoenteringthePowerDownMode,thedevicewillremainidleorinalow-powerstateuntilthelogicconditionoftheselectedwake-uppinonPortA~PortFchangesfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.NotethateachpinonPortA~PortFcanbeselectedindividuallyusingconfigurationop-tionstohavethiswake-upfeature.AdditionallyPortApinshaveanadditionalselectionallowingtheirwake-upfunctiontobeeithernegativeorpositiveedgetriggered.ThisoptionisprovidedusingthePA_WAKE_CTRLreg-ister.OnlyPortApinshavethisfeature,thewake-uppinsontheotherportsareonlynegativeedgetriggered.

Rev.1.1015August5,2011

HT82A836RPortAWake-up

I/OPortControlRegisters

EachI/OporthasitsowncontrolregisterPAC,PBC,PCC,PDC,PECandPFC,tocontroltheinput/outputconfiguration.Withthiscontrolregister,eachCMOSoutputorinputwithorwithoutpull-highresistorstruc-turescanbereconfigureddynamicallyundersoftwarecontrol.EachoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.

FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa²1².Thiswillthenallowthelogicstateoftheinputpintobedi-rectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa²0²,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthatthepro-gramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.Pin-sharedFunctions

Theflexibilityofthemicrocontrollerrangeisgreatlyen-hancedbytheuseofpinsthathavemorethanonefunc-tion.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeover-come.Forsomepins,thechosenfunctionofthemulti-functionI/Opinsissetbyconfigurationoptionswhileforothersthefunctionissetbyapplicationpro-gramcontrol.

·SerialInterface

·ExternalTimer/EventCounterInput

TheexternaltimerpinsTMR0/TMR1arepin-sharedwiththeI/OpinsPC1/PC2.IfthesesharedpinsaretobeusedasaTimer/EventCounterinputs,thentheTimer/EventCountermustbeconfiguredtobeintheEventCounterorPulseWidthMeasurementMode.Thisisachievedbysettingtheappropriatebitsintherelevanttimer/EventCounterControlRegister.Thepinmustalsobesetupasaninputbysettingtheap-propriatebitinthePortControlRegisterPull-highre-sistoroptionscanalsobeselectedviatheappropriateportpull-highconfigurationoption.IfthesharedpinistobeusedasanormalI/Opin,thentheexternaltimerinputfunctionmustbedisabled,byensuringthatthecorrespondingTimer/EventCounterisconfiguredtobeintheOffModeorTimerMode.

·PFDOutput

ThedevicecontainsaPFDfunctionwhosesingleout-putispin-sharedwithPC0.Theoutputfunctionofthispinischosenviasoftware.Notethatthecorrespond-ingbitoftheportcontrolregister,PCC.0,mustsetupthepinasanoutputtoenablethePFDoutput.IfthePCCportcontrolregisterhassetupthepinasanin-put,thenthepinwillfunctionasanormallogicinputwiththeusualpull-highoption,evenifthePFDconfig-urationoptionhasbeenselected.

·SPIInterface

ThedevicecontainsaninternalSPIinterfacewhosepinsaresharedwithI/OpinsPC4~PC7.TheSPIIn-terfacecontrolregister,SBCR,isusedtodetermineifthesepinsaretobeusedasnormalI/OpinsorasSPIInterfacepins.I/OPinStructures

ThefollowingdiagramsillustratetheI/Opininternalstructures.AstheexactlogicalconstructionoftheI/Opinmaydifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.

TheserialinterfacepinsSDO,SDI,SCSandSCKarepin-sharedwiththeI/OpinsPC4,PC5,PC6andPC7.Forapplicationsnotrequiringserialinterface,thepin-sharedpinscanbeusedasanormalI/Opin.

·ExternalInterrupt

TheexternalinterruptpinINTispin-sharedwiththeI/OpinPE7.Forapplicationsnotrequiringanexternalinterruptinput,thepin-sharedexternalinterruptpincanbeusedasanormalI/Opin,howevertodothis,theexternalinterruptenablebitsintheMFI1Cregistermustbedisabled.

Rev.1.1016August5,2011

HT82A836RInput/OutputPorts

ProgrammingConsiderations

Withintheuserprogram,oneofthefirstthingstocon-siderisportinitialisation.Afterareset,allofthedataandportcontrolregisterwillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highoptionshavebeenselected.IfthePAC,PBC,PCC,PDC,PECandPFCportcontrolregisters,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedPA,PB,PC,PD,PEandPFportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalueintotheportcontrolregisterorbyprogrammingindividualbitsintheportcontrolreg-isterusingthe²SET[m].i²and²CLR[m].i²instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenre-writethisdatabacktotheoutputports.

Timer/EventCounters

Theprovisionoftimersformanimportantpartofanymicrocontrollergivingthedesignerameansofcarryingouttimerelatedfunctions.Thedevicecontainstwoin-ternal16-bitcount-uptimerseachofwhichhasthreeop-eratingmodes.Thetimercanbeconfiguredtooperateasageneraltimer,externaleventcounterorasapulsewidthmeasurementdevice.

TherearethreeregistersrelatedtoeachoftheTimer/EventCounters,theseareapairortimerregis-tersandacontrolregister.TheregisterpairsTMR0L/TMR0HandTMR1L/TMR1Hcontainthe16-bittimingvalue.WritingtotheseregisterpairsplacesaninitialstartingvalueintheTimer/EventCounterpreloadregis-terswhilereadingthemretrievesthecontentsoftheTimer/EventCounter.TheTMR0CandTMR1Cregis-tersaretheTimer/EventCountercontrolregisters,whichdefinethetimeroptions,anddetermineshowthetimersaretobeused.ThetimerclocksourcecanbeconfiguredtocomefromtheinternalsystemclocksourceorfromanexternalclockonsharedpinPC1/TMR0andPC2/TMR1.

Read/WriteTiming

Rev.1.1017August5,2011

HT82A836RTimer/EventCounter0StructureTimer/EventCounter1Structure

ConfiguringtheTimer/EventCounterInputClockSource

TheTimer/EventCounter¢sclockcanoriginatefromvar-ioussources.ThesystemclocksourceisusedwhentheTimer/EventCounterisinthetimermodeorinthepulsewidthmeasurementmode.AnexternalclocksourceisusedwhentheTimer/EventCounterisintheeventcountingmode,theclocksourcebeingprovidedontheexternaltimerpin,TMR0orTMR1.DependingupontheconditionoftheT0EorT1Ebit,eachhightolow,orlowtohightransitionontheexternaltimerpinwillincrementthecounterbyone.

TimerRegisters-TMR0H/TMR0L,TMR1L/TMR1HThetimerregisterarespecialfunctionregisterslocatedintheSpecialPurposeDataMemoryandistheplacewheretheactualtimervaluesarestored.Theseregis-tersexistinpairsandareknownasTMR0L/TMR0HandTMR1L/TMR1H.Thevalueinthesetimerregistersin-creasesbyoneeachtimeaninternalclockpulseisre-ceivedoranexternaltransitionoccursontheexternaltimerpin.ThetimerwillcountfromtheinitialvalueloadedbythepreloadregistertothefullcountofFFFFHatwhichpointthetimeroverflowsandaninternalinter-ruptsignalisgenerated.Thetimervaluewillthenbere-

Rev.1.1018August5,2011

HT82A836Rsetwiththeinitialpreloadregistervalueandcontinuecounting.ToachieveamaximumfullrangecountofFFFFHthepreloadregistermustfirstbeclearedtoallzeros.Itshouldbenotedthatafterpower-on,thepreloadregisterwillbeinanunknowncondition.NotethatiftheTimer/EventCounterisswitchedoffanddataiswrittentoitspreloadregister,thisdatawillbeimmedi-atelywrittenintotheactualtimerregister.However,iftheTimer/EventCounterisenabledandcounting,anynewdatawrittenintothepreloaddataregisterduringthisperiodwillremaininthepreloadregisterandwillonlybewrittenintothetimerregisterthenexttimeanoverflowoccurs.

Notethatwritingdatatothelowerbyte8-bitregisters,TMR0L/TMR1L,willonlyputthewrittendataintoanin-ternallower-orderbyte8-bitbuffer,whilewritingtothehighbyte8-bitregisters,TMR0H/TMR1Hwilltransferthespecifieddataandthecontentsofthelower-orderbytebufferintoboththeTMR0/1HandTMR0/1Lregis-ters.TheTimer/EventCounterpreloadregisterismodi-fiedbywritingtotheTMR0/1Hregisters.ReadingtheTMR0H/TMR1HregisterswilllatchthecontentsofboththeTMR0H/TMR1HandtheTMR0L/TMR1Lcounterstothedestinationandthelower-orderbytebuffer.How-everreadingtheTMR0L/TMR1Lwillonlyreadthecon-tentsofthelowbytebuffer.

TimerControlRegister-TMR0C,TMR1C

TheflexiblefeaturesoftheHoltekmicrocontrollerTimer/EventCountersenablethemtooperateinthreedifferentmodes,theoptionsofwhicharedeterminedbythecontentsoftheircontrolregister,whichhasthenameTMR0CandTMR1C.ItistheTimerControlReg-istertogetherwiththeircorrespondingtimerregisterpairthatcontrolthefulloperationoftheTimer/EventCoun-ter.BeforetheTimer/EventCountercanbeused,itisessentialthattheTimerControlRegisterpairisfullypro-grammedwiththerightdatatoensureitscorrectopera-tion,aprocessthatisnormallycarriedoutduringprograminitialisation.TochoosewhichofthethreemodestheTimer/EventCounteristooperatein,eitherinthetimermode,theeventcountingmodeorthepulsewidthmeasurementmode,bits7and6oftheTimerControlRegister,whichareknownasthebitpairTM1/TM0,mustbesettotherequiredlogiclevels.TheTimer/EventCounteron/offbit,whichisbit4oftheTimerControlRegisterandknownasTON,providesthebasicon/offcontroloftheTimer/EventCounter.SettingthebithighallowstheTimer/EventCountertorun,clear-ingthebitstopsitrunning.IftheTimer/EventCounterisintheeventcountorpulsewidthmeasurementmode,theactivetransitionedgeleveltypeisselectedbythelogiclevelofbit3oftheTimercontrolRegisterwhichisknownasTE.

Timer/EventCounter0/1ControlRegister

Rev.1.1019August5,2011

HT82A836RConfiguringtheTimerMode

Inthismode,thetimercanbeutilisedtomeasurefixedtimeintervals,providinganinternalinterruptsignaleachtimethecounteroverflows.Tooperateinthismode,bitsTM1andTM0oftheTMRCregistermustbesetto1and0respectively.Inthismode,theinternalclockisusedasthetimerclock.TheinputclockfrequencytothetimerisfSYS/4.Thetimer-onbit,TON,mustbesethightoenablethetimertorun.Eachtimeaninternalclockhightolowtransitionoccurs,thetimerincrementsbyone.Whenthetimerisfullandoverflows,thetimerwillberesettothevaluealreadyloadedintothepreloadregisterandcontinuecounting.Ifthetimerinterruptisenabled,anin-terruptsignalwillalsobegenerated.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitintheInterruptControlRegister,INTC0,isresettozero.

ConfiguringtheEventCounterMode

Inthismode,anumberofexternallychanginglogicevents,occurringontheexternaltimerpin,canbere-cordedbytheTimer/EventCounter.Tooperateinthismode,theOperatingModeSelectbitpairintheTimerControlRegistermustbesettothecorrectvalue.InthismodetheexternaltimerpinisusedastheTimer/EventCounterclocksource.AftertheotherbitsintheTimerControlRegisterhavebeensetup,theenablebit,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCountertorun.IftheActiveEdgeSelectbit,whichisbit3oftheTimerControlReg-ister,islow,theTimer/EventCounterwillincrementeachtimetheexternaltimerpinreceivesalowtohightransition.IftheActiveEdgeSelectbitishigh,thecoun-terwillincrementeachtimetheexternaltimerpinre-ceivesahightolowtransition.Whenitisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitintheInterruptControlRegister,INTC0,isresettozero.

AstheexternaltimerpinissharedwithanI/Opin,toen-surethatthepinisconfiguredtooperateasaneventcounterinputpin,twothingshavetohappen.ThefirstistoensurethattheOperatingModeSelectbitsintheTimerControlRegisterplacetheTimer/EventCounterintheEventCountingMode,thesecondistoensurethattheportcontrolregisterconfiguresthepinasaninput.Itshouldbenotedthatintheeventcountingmode,evenifthemicrocontrollerisinthePowerDownMode,theTimer/EventCounterwillcontinuetorecordexternallychanginglogiceventsonthetimerinputpin.Asaresultwhenthetimeroverflowsitwillgenerateatimerinterruptandcorrespondingwake-upsource.

ConfiguringthePulseWidthMeasurementModeInthismode,theTimer/EventCountercanbeutilisedtomeasurethewidthofexternalpulsesappliedtotheex-ternaltimerpin.Tooperateinthismode,theOperatingModeSelectbitpairintheTimerControlRegistermustbesettothecorrectvalue.Inthismodetheinternalclock,fSYS/4,isusedastheTimer/EventCounterclock.AftertheotherbitsintheTimerControlRegisterhavebeensetup,theenablebit,whichisbit4oftheTimerControlRegister,canbesethightoenabletheTimer/EventCounter,howeveritwillnotactuallystartcountinguntilanactiveedgeisreceivedontheexternaltimerpin.

IftheActiveEdgeSelectbit,whichisbit3oftheTimerControlRegister,islow,onceahightolowtransitionhasbeenreceivedontheexternaltimerpin,theTimer/EventCounterwillstartcountinguntiltheexternaltimerpinre-turnstoitsoriginalhighlevel.AtthispointtheenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.IftheActiveEdgeSelectbitishigh,theTimer/EventCounterwillbegincountingoncealowtohightransitionhasbeenreceivedontheexternaltimerpinandstopcountingwhentheexternaltimerpinreturnstoitsoriginallowlevel.Asbefore,theenablebitwillbeautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.ItisimportanttonotethatinthePulseWidthMeasurementMode,the

TimerModeTimingChart

EventCounterModeTimingChart

Rev.1.1020August5,2011

HT82A836Renablebitisautomaticallyresettozerowhentheexter-nalcontrolsignalontheexternaltimerpinreturnstoitsoriginallevel,whereasintheothertwomodestheen-ablebitcanonlyberesettozerounderprogramcontrol.TheresidualvalueintheTimer/EventCounter,whichcannowbereadbytheprogram,thereforerepresentsthelengthofthepulsereceivedontheexternaltimerpin.Astheenablebithasnowbeenreset,anyfurthertransitionsontheexternaltimerpinwillbeignored.Notuntiltheenablebitisagainsethighbytheprogramcanthetimerbeginfurtherpulsewidthmeasurements.Inthisway,singleshotpulsemeasurementscanbeeasilymade.

ItshouldbenotedthatinthismodetheTimer/EventCounteriscontrolledbylogicaltransitionsontheexter-naltimerpinandnotbythelogiclevel.WhentheTimer/EventCounterisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounterwillre-loadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.TheinterruptcanbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitintheInterruptControlRegister,INTC0,isresettozero.

AstheexternaltimerpinissharedwithanI/Opin,toen-surethatthepinisconfiguredtooperateasapulsewidthmeasurementpin,twothingshavetohappen.ThefirstistoensurethattheOperatingModeSelectbitsintheTimerControlRegisterplacetheTimer/EventCoun-terinthePulseWidthMeasurementMode,thesecondistoensurethattheportcontrolregisterconfiguresthepinasaninput.I/OInterfacing

TheTimer/EventCounter,whenconfiguredtorunintheeventcounterorpulsewidthmeasurementmode,re-quirestheuseofanexternalpinforcorrectoperation.Astheexternaltimerpinispin-sharedwithanI/Opin,itmustbeconfiguredcorrectlytoensureitissetupforuseasaTimer/EventCounterinputandnotasanormalI/Opin.Thisisimplementedbyensuringthatthemodese-lectbitsintheTimer/EventCountercontrolregister,se-lecteithertheeventcounterorpulsewidthmeasurementmode.AdditionallythePortControlReg-isterbitforthispinmustbesethightoensurethatthepinissetupasaninput.Anypull-highconfigurationforthispinswillremainvalidevenifthepinisusedasaTimer/EventCounterinput.ProgrammingConsiderations

Whenconfiguredtoruninthetimermode,thefSYS/4isusedasthetimerclocksourceandisthereforesynchro-nisedwiththeoveralloperationofthemicrocontroller.Inthismode,whentheappropriatetimerregisterisfull,themicrocontrollerwillgenerateaninternalinterruptsignaldirectingtheprogramflowtotherespectiveinternalin-terruptvector.Forthepulsewidthmeasurementmode,thefSYS/4clockisalsousedasthetimerclocksourcebutthetimerwillonlyrunwhenthecorrectlogiccondi-tionappearsontheexternaltimerinputpin.Asthisisanexternaleventandnotsynchronizedwiththeinternaltimerclock,themicrocontrollerwillonlyseethisexternaleventwhenthenexttimerclockpulsearrives.Asare-sulttheremaybesmalldifferencesinmeasuredvaluesrequiringprogrammerstotakethisintoaccountduringprogramming.Thesameappliesifthetimerisconfig-uredtobeintheeventcountingmodewhichagainisanexternaleventandnotsynchronisedwiththefSYS/4clock.

WhentheTimer/EventCounterisreadorifdataiswrit-tentothepreloadregisters,theclockisinhibitedtoavoiderrors,howeverasthismayresultinacountinger-ror,thisshouldbetakenintoaccountbytheprogram-mer.Caremustbetakentoensurethatthetimersareproperlyinitialisedbeforeusingthemforthefirsttime.Theassociatedtimerenablebitsintheinterruptcontrolregistermustbeproperlysetotherwisetheinternalin-terruptassociatedwiththetimerwillremaininactive.Theedgeselect,timermodeandclocksourcecontrolbitsintimercontrolregistermustalsobecorrectlysettoensurethetimerisproperlyconfiguredfortherequiredapplication.Itisalsoimportanttoensurethataninitialvalueisfirstloadedintothetimerregisterbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvalueofthetimerregisterisunknown.Afterthetimerhasbeeninitialisedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolregis-ter.Notethatsettingthetimerenablebithightoturnthetimeron,shouldonlybeexecutedafterthetimermode

PulseWidthMeasureModeTimingChart

Rev.1.1021August5,2011

HT82A836Rbitshavebeenproperlysetup.Settingthetimerenablebithightogetherwithamodebitmodification,mayleadtoimpropertimeroperationifexecutedasasingletimercontrolregisterbytewriteinstruction.WhentheTimer/Eventcounteroverflows,itscorrespondinginter-ruptrequestflagintheinterruptcontrolregisterwillbeset.Ifthetimerinterruptisenabledthiswillinturngener-ateaninterruptsignal.Howeverirrespectiveofwhetherthetimerinterruptisenabledornot,aTimer/Eventcounteroverflowwillalsogenerateawake-upsignalifthedeviceisinaPower-downcondition.ThissituationmayoccuriftheTimer/EventCounterisintheEventCountingModeandiftheexternalsignalcontinuestochangestate.Insuchacase,theTimer/EventCounterwillcontinuetocounttheseexternaleventsandifanoverflowoccursthedevicewillbewokenupfromits

Power-downcondition.Topreventsuchawake-upfromoccurring,thetimerinterruptrequestflagshouldfirstbesethighbeforeissuingtheHALTinstructiontoenterthePowerDownMode.TimerProgramExample

ThisprogramexampleshowshowtheTimer/EventCounterregistersaresetup,alongwithhowtheinter-ruptsareenabledandmanaged.NotehowtheTimer/EventCounteristurnedon,bysettingbit4oftheTimerControlRegister.TheTimer/EventCountercanbeturnedoffinasimilarwaybyclearingthesamebit.ThisexampleprogramsetstheTimer/EventCountertobeinthetimermode,whichusestheinternalsystemclockastheclocksource.

org04h;usbinterruptvectorjmpusbintretiorg08h;Timer/EventCounter0interruptvectorjmptmr0int;jumpherewhenTimer0overflows:

org20h;mainprogram

;internalTimer/EventCounterinterruptroutinetmr0int::

;Timer/EventCounter0mainprogramplacedhere:reti::

begin:

;setupTimer0registersmova,09bh;setuppreloadvalue-timer0countsfromthisvaluetoFFFFHmovtmr0l,a;mova,00hmovtmr0h,a;mova,080h;setupTimer0controlregistermovtmr0c,a;timermode;setupinterruptregistermova,005h;enablemasterinterruptandtimerinterruptmovintc0,asettmr0c.4;startTimer0-notemodebitsmustbepreviouslysetup

Rev.1.1022August5,2011

HT82A836RProgrammableFrequencyDivider-PFD

TheProgrammableFrequencyDividerfunction,PFD,allowsthegenerationofauserdefinedfrequency.TheclocksourceforthePFDisthesystemclockdividedby4,whichafterbeingdividedby16isthenpassedthroughaprogrammableprescalerandthePFDDregis-terallowsarangeofuserdefinedfrequenciestobegen-erated.

OveralloperationofthePFDiscontrolledusingtworeg-isters,thePFDCregisterandthePFDDregister.AsthePFDoutputpinispin-sharedwithI/OpinPC0,thePFD_IObitinthePFDCregisterisusedtoselectwhetherthepinistobeusedananormalI/Ofunctionor

tobeusedasaPFDoutput.ThePFDENbitisusedtocontroltheoverallon/offfunctionofthePFD,whilebitsPRES0andPRES1areusedtoselectthefrequencydi-visionratiooftheprescaler.ThePFDDregisterprovidedfurtherdivisionoftheclocksource,howeverthisregistercanonlybewrittentowhenthePFDfunctionisenabled.IfthePFDfunctionisdisabled,thenallwriteoperationstothePFDDregisterwillbeinhibited.WhenthePFDisdisablednotethatthePFDDregisterwillbeautomati-callycleared.ThePFDDcontents,thePFDmustbeen-abled.Whenthegeneratorisdisabled,thePFDDisclearedbyhardware.

PFDBlockDiagram

PFDCRegister

ThegeneratedfrequencyofthePFDfunctionisgivenbythefollowingformula:

PowerAmplifier

TheSELWbitinthePFDCregisterisusedtocontrolthepoweramplifierinputsource.ThesoftwareshouldsetSELW=²1²whenthepoweramplifiersignalcomefromMUSIC_IN,otherwisethespeakeroutputUSBAudiodata.

Rev.1.1023August5,2011

HT82A836RInterrupts

Interruptsareanimportantpartofanymicrocontrollersystem.WhenaUSBInterrupt,play/recorddatavalidin-terrupt,aTimer/EventCounteroverflow,receptionofSPIdata,A/DInterruptorExternalInterruptisoccurs,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.ThedeviceprovidesaUSBinterrupt,twointer-naltimer/eventcounterinterrupts,aplay/recorddatavalidinterruptandaMultifunctioninterrupt.ThislatterMulti-functionInterruptrepresentstheSerialInterfaceInterrupt,A/DInterruptortheExternalInterrupt.InterruptRegisters

Overallinterruptcontrol,whichmeansinterruptenablingandrequestflagsetting,iscontrolledbythreeinterruptcontrolregistersINTC0,INTC1andMFI1Cwhicharelo-catedintheDataMemory.Bycontrollingtheappropriateenablebitsinthisregistereachindividualinterruptcanbeenabledordisabled.Alsowhenaninterruptoccurs,thecorrespondingrequestflagwillbesetbythemicrocontroller.Theglobalenableflagifclearedtozerowilldisableallinterrupts.InterruptOperation

AUSBinterrupt,aPlayorRecorddatavalidinterrupt,aTimer/EventCounteroverflow,anSPIinterrupt,anA/Dconversioncompleteinterruptoranactiveedgeontheexternalinterruptpinwillallgenerateaninterruptre-questbysettingtheircorrespondingrequestflag,iftheirappropriateinterruptenablebitisset.Whenthishap-pens,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorre-spondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.TheinstructionatthisvectorwillusuallybeaJMPstatementwhichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinter-ruptserviceroutinemustbeterminatedwithaRETIstatement,whichretrievestheoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollerto

continuewithnormalexecutionatthepointwherethein-terruptoccurred.Thevariousinterruptenablebits,to-getherwiththeirassociatedrequestflags,areshowninthefollowingdiagramwiththeirorderofpriority.Onceaninterruptsubroutineisserviced,alltheotherinter-ruptswillbeblocked,astheEMIbitwillbeclearedauto-matically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However,ifotherinterruptrequestsoc-curduringthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillbere-corded.Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtherou-tine,toallowinterruptnesting.Ifthestackisfull,thein-terruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.InterruptPriority

Interrupts,occurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginter-ruptsareenabled.Incaseofsimultaneousrequests,thefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.No.abcdefInterruptSourceUSBInterruptTimer/EventCounter0overflowTimer/EventCounter1overflowPlayInterruptMultifunction1interruptsubrou-tine:SerialInterfaceInterrupt,A/DInterrupt,ExternalInterruptRecordInterruptPriorityVector12345604H08H0CH10H14H18HIncaseswherebothUSBandPlayinterruptsareen-abledandwhereanUSBandPlayinterruptoccurssi-multaneously,theUSBinterruptwillalwayshavepriorityandwillthereforebeservicedfirst.Suitablemaskingoftheindividualinterruptsusingtheinterruptregisterscanpreventsimultaneousoccurrences.

Rev.1.1024August5,2011

HT82A836RINTC0Register

INTC1Register

Rev.1.1025August5,2011

HT82A836RInterruptStructure

USBInterrupt

TheUSBinterruptwillbetriggeredbyanyofthefollow-ingUSBeventsresultingintherelatedinterruptrequestflag,USBF;bit4ofINTC0,beingset:

·APCaccessofthecorrespondingUSBFIFO·AUSBsuspendsignalfromthePC·AUSBresumesignalfromthePC·AUSBResetsignal

Timer/EventCounterInterrupt

ForaTimer/EventCounterinterrupttooccur,theglobalinterruptenablebit,EMI,andthecorrespondingtimerinterruptenablebit,ET0IorET1I,mustfirstbeset.AnactualTimer/EventCounterinterruptwilltakeplacewhentheTimer/EventCounterrequestflag,T0ForT1F,isset,asituationthatwilloccurwhentherelevantTimer/EventCounteroverflows.Whentheinterruptisenabled,thestackisnotfullandaTimer/EventCounter0overflowoccurs,asubroutinecalltothetimer0inter-ruptvectoratlocation08H,willtakeplace.IfaTimer/EventCounter1overflowoccurs,asubroutinecalltothetimer1interruptvectoratlocation0CHwilltakeplace.Whentheinterruptisserviced,thetimerin-terruptrequestflag,T0ForT1F,willbeautomaticallyre-setandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.PlayInterrupt

ForaPlayInterrupttooccur,theglobalinterruptenablebit,,andthecorrespondingPlayInterruptbit,EPLAI,mustfirstbeset.AnactualPlayInterruptwilltakeplacewhenthePlayInterruptrequestflag,PLAYF,isset,asit-uationthatwilloccurataregularplayfrequencyof8kHzifthePLAY_MODEbitintheMODE_CTRLregisteris

Whentheinterruptisenabled,thestackisnotfullandtheinterruptisactive,asubroutinecalltolocation04Hwilloccur.Theinterruptrequestflag,USBF,andEMIbitswillbeclearedtodisableotherinterrupts.WhenthePCHostaccessestheHT82A836RFIFO,thecorrespond-ingUSRrequestbitisset,andaUSBinterruptistrig-gered.InthiswaytheusercandeterminewhichFIFOhasbeenaccessed.Whentheinterrupthasbeenser-viced,thecorrespondingbitwillbeautomaticallycleared.WhentheHT82A836RreceivesaUSBSus-pendsignalfromthehostPC,thesuspendline,bit0oftheUSCregister,intheHT82A836RissetandaUSBinterruptisalsotriggered.Alsowhenthedevicere-ceivesaResumesignalfromthehostPC,theresumeline,bit3oftheUSCregister,issetandaUSBinterruptgenerated.

Rev.1.1026August5,2011

HT82A836Rsethigh.Ifthisbitisnothigh,thentheplayinterruptfre-quencywillbe48kHz.Whentheinterruptisenabled,thestackisnotfullandaPlayInterruptoccurs,asubroutinecalltothePlayInterruptvectoratlocation10H,willtakeplace.Whentheinterruptisserviced,thePlayInterruptrequestflag,PLAYF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherin-terrupts.

MultiFunctionInterrupt

AnadditionalinterruptknownastheMulti-functioninter-ruptisprovided.Unliketheotherinterrupts,thisinterrupthasnoindependentsource,butratherisformedfromthreeotherexistinginterruptsources,namelytheSerialInterfaceinterrupt,theA/DConverterinterruptandtheExternalinterrupt.TheMulti-functioninterruptisen-abledbysettingtheEMF1Ibit,whichisbit1oftheINTC1register.AnactualMulti-functioninterruptwillbeinitialisedwhentheMulti-functioninterruptrequestflagMFF1isset,thisisbit5oftheINTC1register.Whenthemasterinterruptglobalbitisset,thestackisnotfullandthecorrespondingEMF1Iinterruptenablebitisset,aMulti-FunctioninternalinterruptwillbegeneratedwheneitheraSerialInterfaceInterrupt,anA/DConverterIn-terruptoranExternalInterruptoccurs.Thiswillcreateasubroutinecalltoitscorrespondingvectorlocation014H.WhenaMulti-functioninternalinterruptoccurs,theMulti-FunctionrequestflagMFF1willberesetandtheEMIbitwillbeclearedtodisableotherinterrupts.However,itmustbenotedthattherequestflagsfromtheoriginalsourceoftheMulti-functioninterrupt,namelytheSerialInterfaceInterrupt,theA/DConverterortheExternalInterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheuser.

ExternalInterrupt

Thedevicecontainsanexternalinterruptfunctioncon-trolledbytheexternalpinINT.Foranexternalinterrupttooccur,thepinmustbesetupasaninterruptinputpinbyensuringthatthecorrespondingexternalinterruptenablebitisfirstset.Thisisbit2intheMFI1CregisterandknownasEEI.AnexternalinterruptistriggeredbyanegativeedgetransitionontheexternalinterruptpinINT,afterwhichtherelatedinterruptrequestflag,EIF,whichisbit6intheMFI1Cregister,willbeset.Theinter-ruptvectorfortheExternalInterruptistheMulti-functioninterruptlocatedat014H.ThereforeiftheMulti-functionandExternalInterruptsareenabled,thestackisnotfullandanegativelogicaltransitionoccursonpinINT,asubroutinecalltolocation014Hwilltakeplace.TheMulti-functionInterruptrequestflagMFF1willberesetautomaticallyandtheEMIbitwillbeclearedtodisableotherinterrupts.TheExternalInterruptflagwillnotberesetautomaticallyandneedstoberesetmanuallybytheapplicationprogram.TheexternalinterruptpinINTispin-sharedwithI/OpinPE7andcanonlybeconfig-uredasexternalinterruptpinsiftheinterruptisenabledandifthepinisprogrammedasaninputpins.A/DConverterInterrupt

ThedevicecontainsaninternalA/Dconverterwithitsowninterruptfunction.ForanA/DInterrupttooccur,thecorrespondingA/DInterruptenablebitmustbefirstset.Thisisbit1intheMFI1CregisterandknownasEADI.AnA/DInterruptisgeneratedwhentheA/Dconversionprocessiscomplete,afterwhichtherelatedinterruptre-questflag,ADF,whichisbit5intheMFI1Cregister,willbeset.TheinterruptvectorfortheA/DInterruptistheMulti-functioninterruptlocatedat014H.ThereforeiftheMulti-functionandA/DInterruptareenabled,thestackis

MFI1CRegister

Rev.1.1027August5,2011

HT82A836RnotfullandtheA/Dconversioncompletes,asubroutinecalltolocation014Hwilltakeplace.TheMulti-functionInterruptrequestflagMFF1willberesetautomaticallyandtheEMIbitwillbeclearedtodisableotherinter-rupts.TheA/DInterruptflagwillnotberesetautomati-callyandneedstoberesetmanuallybytheapplicationprogram.

SerialInterfaceInterrupt

ThedevicecontainsaninternalSerialInterfacewithitsowninterruptfunction.ForaSerialInterfaceInterrupttooccur,thecorrespondingSerialInterfaceInterrupten-ablebitmustbefirstset.Thisisbit0intheMFI1Cregis-terandknownasESII.ASerialInterfaceInterruptisgeneratedwhenadatareceptionortransmissioniscomplete,afterwhichtherelatedinterruptrequestflag,SIF,whichisbit4intheMFI1Cregister,willbeset.TheinterruptvectorfortheSerialInterfaceInterruptistheMulti-functionInterrupt,locatedat014H.ThereforeiftheMulti-functionandSerialInterfaceInterruptareenabled,thestackisnotfullandaserialinterfacedatareceptionortransmissioniscomplete,asubroutinecalltolocation014Hwilltakeplace.TheMulti-functionInterruptre-questflagMFF1willberesetautomaticallyandtheEMIbitwillbeclearedtodisableotherinterrupts.TheSerialInterfaceInterruptflagwillnotberesetautomaticallyandneedstoberesetmanuallybytheapplicationpro-gram.

RecordInterrupt

ForaRecordInterrupttooccur,theglobalinterrupten-ablebit,EMI,andthecorrespondingRecordInterruptbit,RECI,mustfirstbeset.AnactualRecordInterruptwilltakeplacewhentheRecordInterruptrequestflag,RECF,isset,asituationthatwilloccurwhentherecorddataisvalid.Whentheinterruptisenabled,thestackisnotfullandaRecordInterruptoccurs,asubroutinecalltotheRecordInterruptvectoratlocation18H,willtakeplace.Whentheinterruptisserviced,theRecordInter-ruptrequestflag,RECF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.IftheA/DConverterispowereddown(AD_ENB=1),PLLclockdisabled(PLLEN=1)orUSBclockdisabled(USBCKEN=0),therecordinterruptalsobedisabled.

ProgrammingConsiderations

Bydisablingtheinterruptenablebits,arequestedinter-ruptcanbepreventedfrombeingserviced,however,onceaninterruptrequestflagisset,itwillremaininthisconditionintheinterruptcontrolregisteruntilthecorre-spondinginterruptisservicedoruntiltherequestflagisclearedbyasoftwareinstruction.

Itisrecommendedthatprogramsdonotusethe²CALLsubroutine²instructionwithintheinterruptsubroutine.Interruptsoftenoccurinanunpredictablemanneror

needtobeservicedimmediatelyinsomeapplications.Ifonlyonestackisleftandtheinterruptisnotwellcon-trolled,theoriginalcontrolsequencewillbedamagedoncea²CALLsubroutine²isexecutedintheinterruptsubroutine.

AlloftheseinterruptshavethecapabilityofwakinguptheprocessorwheninthePowerDownMode.OnlytheProgramCounterispushedontothestack.Ifthecon-tentsoftheaccumulatororstatusregisterarealteredbytheinterruptserviceprogram,whichmaycorruptthede-siredcontrolsequence,thenthecontentsshouldbesavedinadvance.

ResetandInitialisation

Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbesettosomepredeterminedconditionirrespectiveofoutsideparameters.Themostimportantresetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywillensurethatthemicrocontroller,af-terashortdelay,willbeinawelldefinedstateandreadytoexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcom-mences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereitisnecessarytoforcefullyapplyaresetconditionwhenthemicrocontrollerisrunning.Oneexampleofthisiswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESETlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someofthemicrocontrollerregistersremainunchangedallowingthemicrocontrollertopro-ceedwithnormaloperationaftertheresetlineisallowedtoreturnhigh.AnothertypeofresetiswhentheWatch-dogTimeroverflowsandresetsthemicrocontroller.Alltypesofresetoperationsresultindifferentregistercon-ditionsbeingsetup.

AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESETresetisim-plementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.ResetFunctions

Therearefivewaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringbothinternallyandex-ternally:

·Power-onReset

Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryad-

Rev.1.1028August5,2011

HT82A836Rdress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

AlthoughthemicrocontrollerhasaninternalRCresetfunction,iftheVDDpowersupplyrisetimeisnotfastenoughordoesnotstabilisequicklyatpower-on,theinternalresetfunctionmaybeincapableofprovidingproperresetoperation.Forthisreasonitisrecom-mendedthatanexternalRCnetworkisconnectedtotheRESETpin,whoseadditionaltimedelaywillen-surethattheRESETpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeinhibited.AftertheRESETlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

Counterwillresettozeroandprogramexecutioniniti-atedfromthispoint.

RESResetTimingChart

·LowVoltageReset-LVR

Themicrocontrollercontainsalowvoltageresetcir-cuitinordertomonitorthesupplyvoltageofthede-vice,whichisselectedviaaconfigurationoption.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedevicein-ternally.TheLVRincludesthefollowingspecifica-tions:ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.char-acteristics.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitandwillnotperformaresetfunction.

Power-OnResetTimingChart

FormostapplicationsaresistorconnectedbetweenVDDandtheRESETpinandacapacitorconnectedbetweenVSSandtheRESETpinwillprovideasuit-ableexternalresetcircuit.AnywiringconnectedtotheRESETpinshouldbekeptasshortaspossibletomin-imizeanystraynoiseinterference.

LowVoltageResetTimingChart

·WatchdogTime-outResetduringNormalOperation

TheWatchdogtime-outResetduringnormalopera-tionisthesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto²1².

BasicResetCircuit

ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCir-cuitshownisrecommended.

WDTTime-outResetduringNormalOperation

TimingChart

·WatchdogTime-outResetduringPowerDown

TheWatchdogtime-outResetduringPowerDownisalittledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthatthePro-gramCounterandtheStackPointerwillbeclearedto²0²andtheTOflagwillbesetto²1².RefertotheA.C.CharacteristicsfortSSTdetails.

EnhancedResetCircuit

·RESPinReset

ThistypeofresetoccurswhenthemicrocontrollerisalreadyrunningandtheRESETpinisforcefullypulledlowbyexternalhardwaresuchasanexternalswitch.Inthiscaseasinthecaseofotherreset,theProgramRev.1.10

29

WDTTime-outResetduringPowerDown

TimingChart

August5,2011

HT82A836RResetInitialConditions

Thedifferenttypesofresetdescribedaffecttheresetflagsindifferentways.Theseflags,knownasPDFandTOarelocatedinthestatusregisterandarecontrolledbyvariousmicrocontrolleroperations,suchasthePowerDownfunctionorWatchdogTimer.Theresetflagsareshowninthetable:TOPDF0u110uu1RESETConditionsRESresetduringpower-onRESorLVRresetduringnormaloperationWDTtime-outresetduringnormaloperationWDTtime-outresetduringPowerDownStackPointerThefollowingtableindicatesthewayinwhichthevari-ouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

ItemProgramCounterInterruptsWDTConditionAfterRESETResettozeroAllinterruptswillbedisabledClearafterreset,WDTbeginscountingTimer/EventCounterTimerCounterwillbeturnedoffInput/OutputPortsI/OportswillbesetupasinputsStackPointerwillpointtothetopofthestackNote:²u²standsforunchanged

Thedifferentkindsofresetsallaffecttheinternalregis-tersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrollerisinafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.Notethatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Thestatesoftheregistersaresummarizedinthetable.

Reset(Power-on)xxxxxxxxxxxxxxxxxxxxxxxx000Hxxxxxxxx-xxxxxxx00000111--00xxxx-0000000xxxxxxxxxxxxxxxx00-01000xxxxxxxxxxxxxxxx00-01---1111111111111111WDTRESResetRESResetTime-out(Normal(HALT)(NormalOperation)Operation)uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuu00000111--1uuuuu-0000000uuuuuuuuuuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---1111111111111111uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuu00000111--uuuuuu-0000000uuuuuuuuuuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---1111111111111111uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuu00000111--01uuuu-0000000uuuuuuuuuuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---1111111111111111WDTTime-Out(HALT)*uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuuuuuuuuuu--11uuuu-uuuuuuuuuuuuuuuuuuuuuuuuu-uuuuuuuuuuuuuuuuuuuuuuu-uu---uuuuuuuuuuuuuuuuUSBResetUSBReset(Normal)(HALT)uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuu00000111--uuuuuu-0000000uuuuuuuuuuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---1111111111111111uuuuuuuuuuuuuuuuuuuuuuuu000Huuuuuuuu-uuuuuuu00000111--01uuuu-0000000uuuuuuuuuuuuuuuu00-01000uuuuuuuuuuuuuuuu00-01---1111111111111111RegisterMP0MP1ACCProgramCounterTBLPTBLHWDTSSTATUSINTC0TMR0HTMR0LTMR0CTMR1HTMR1LTMR1CPAPACRev.1.1030August5,2011

HT82A836RWDTRESResetRESResetResetTime-out(Normal(HALT)(Power-on)(NormalOperation)Operation)1111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000xxxxxxxx10000000000000000000000000000000000000000000000000000000xxxxx010xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000000000000000000000000000000000000000000001100000uuuuuuuu0000000000000000000000001111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000uuuuuuuuuuxxuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxxxx010uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu000000000000000000000000000000000000000000000000000000000000000001100000uuuuuuuu0000000000000000000000001111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000uuuuuuuu10xx0000000000000000000000000000000000000000000000000000xxxxx010uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu000000000000000000000000000000000000000000000000000000000000000001100000uuuuuuuu0000000000000000000000001111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000uuuuuuuu10xx0000000000000000000000000000000000000000000000000000xxxxx010uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu000000000000000000000000000000000000000000000000000000000000000001100000uuuuuuuu000000000000000000000000WDTTime-Out(HALT)*uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu----uuuu----uuuu-uuuuuuuuuuuuuuu10xxuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuxxxxx010uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu000000000000000000000000uuuuuuuu00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuUSBResetUSBReset(Normal)(HALT)1111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000uuuuuuuu10000u0000uu00000u00u00000000000000000000u00u00000000000xxxxx010000000000000000000000000000000000000000000000000000000000000000000uuuuuu0uuu00000uuu0000uuuuuuuu00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu1111111111111111111111111111111111111111111111111111111111111111----1111----1111-0000000uuuuuuuu10000u0000uu00000u00u00000000000000000000u00u00000000000xxxxx010000000000000000000000000000000000000000000000000000000000000000000uuuuuu0uuu00000uuu0000uuuuuuuu00000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuRegisterPBPBCPCPCCPDPDCPEPECPFPFCINTC1TBHPUSCUSRUCCAWRSTALLSIESMISCSETIOFIFO0FIFO1FIFO2FIFO3FIFO4DAC_LIMIT_LDAC_LIMIT_HDAC_WRPGA_CTRLPFDCPFDDOPER_MODEMODE_CTRLSBCRSBDRRECORD_IN_LRECORD_IN_HPLAY_DATAL_LRev.1.1031August5,2011

HT82A836RWDTRESResetRESResetResetTime-out(Normal(HALT)(Power-on)(NormalOperation)Operation)0000000000000000000000000000000000000000xxxxxxxxxxxxxxxx010000001-----000000000000000000xxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxx010000001-----000000000000000000xxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxx010000001-----000000000000000000xxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxx010000001-----000000000000000000xxxxxxxxxxxxxxxx000000000000000000000000WDTTime-Out(HALT)*uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuUSBResetUSBReset(Normal)(HALT)uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu00000000uuuuuuuu00000000uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu-----uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuu00000000uuuuuuuu00000000RegisterPLAY_DATAL_HPLAY_DATAR_LPLAY_DATAR_HRECORD_DATA_LRECORD_DATA_HADRLADRHADCRACSRPA_WAKE_CTRLPWMCPWM0PWM1MFI1CUSB_STATEUSVC²*²standsforwarmreset

²u²standsforunchanged²x²standsforunknown

²-²standsforunimplemented

Oscillator

Thedeviceusecrystaloscillatorasthesystemclocksource.TwotypesofcrystalsystemclockfrequenciescanbeselectedwhilevariousclocksourceoptionsfortheWatchdogTimerareprovidedformaximumflexibil-ity.

SystemCrystal/CeramicOscillator

Forthe12MHzcrystaloscillatorconfigurations,thesim-pleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscil-lation.Forthe6MHzcrystaloscillatorconfigurationtheadditionoftwosmallvaluecapacitorsarerequired.TheSYSCLKbitintheUCCregisterdeterminesthesystemfrequencyselection.Crystal6MHzCrystal12MHzCrystalC1,C222pFNCCrystal/CeramicOscillator

WatchdogTimerOscillator

TheWDToscillatorisafullyself-containedfreerunningon-chipRCoscillatorwithatypicalperiodof65usat5Vrequiringnoexternalcomponents.Whenthedeviceen-tersthePowerDownMode,thesystemclockwillstoprunningbuttheWDToscillatorcontinuestofree-runandtokeepthewatchdogactive.However,topreservepowerincertainapplicationstheWDToscillatorcanbedisabledviaaconfigurationoption.

Rev.1.1032August5,2011

HT82A836RPowerDownModeandWake-up

PowerDownMode

AlloftheHoltekmicrocontrollershavetheabilitytoenteraPowerDownMode,alsoknownastheHALTModeorSleepMode.Whenthedeviceentersthismode,thenor-maloperatingcurrent,willbereducedtoanextremelylowstandbycurrentlevel.ThisoccursbecausewhenthedeviceentersthePowerDownMode,thesystemoscillatorisstoppedwhichreducesthepowerconsump-tiontoextremelylowlevels,however,asthedevicemaintainsitspresentinternalcondition,itcanbewokenupatalaterstageandcontinuerunning,withoutrequir-ingafullreset.Thisfeatureisextremelyimportantinap-plicationareaswheretheMCUmusthaveitspowersupplyconstantlymaintainedtokeepthedeviceinaknownconditionbutwherethepowersupplycapacityislimitedsuchasinbatteryapplications.EnteringthePowerDownMode

ThereisonlyonewayforthedevicetoenterthePowerDownModeandthatistoexecutethe²HALT²instruc-tionintheapplicationprogram.Whenthisinstructionisexecuted,thefollowingwilloccur:

·Thesystemoscillatorwillstoprunningandtheappli-

inputs.AlsonotethatadditionalstandbycurrentwillalsoberequirediftheconfigurationoptionshaveenabledtheWatchdogTimerinternaloscillator.Wake-up

AfterthesystementersthePowerDownMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

·Anexternalreset

·AnexternalfallingorrisingedgeonPortA·AnexternalfallingedgeonPortB~PortF·Asysteminterrupt·AWDToverflow

cationprogramwillstopatthe²HALT²instruction.

·TheDataMemorycontentsandregisterswillmaintain

theirpresentcondition.

·TheWDTwillbeclearedandresumecountingifthe

Ifthesystemiswokenupbyanexternalreset,thede-vicewillexperienceafullsystemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theac-tualsourceofthewake-upcanbedeterminedbyexam-iningtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe²HALT²instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupviaanindividualconfig-urationoptiontopermitanegative(orpositive)transitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe²HALT²instruction.Eachpinoncanbesetupviaanindividualconfigurationoptiontopermitanegativetransitiononthepintowake-upthesystem.PortAhasanadditionfunction,controlledviathePA_WAKE_CTRLregisterintheDataMemory,allowingeitheranegativeorpositiveedgetoinitiateaWake-upfunction.Anyexternalpinwake-upwillcausethesystemtoresumeexecutionatthein-structionfollowingthe²HALT²instruction.

Ifthesystemiswokenupbyaninterrupt,thentwopossi-blesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexe-cutionattheinstructionfollowingthe²HALT²instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeser-vicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflagissetto²1²be-foreenteringthePowerDownMode,thewake-upfunc-tionoftherelatedinterruptwillbedisabled.

WDTclocksourceisselectedtocomefromtheWDToscillator.TheWDTwillstopifitsclocksourceorigi-natesfromthesystemclock.

·TheI/Oportswillmaintaintheirpresentcondition.·Inthestatusregister,thePowerDownflag,PDF,will

besetandtheWatchdogtime-outflag,TO,willbecleared.

StandbyCurrentConsiderations

AsthemainreasonforenteringthePowerDownModeistokeepthecurrentconsumptionoftheMCUtoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-amps,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimized.Specialatten-tionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcur-rentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeundonbedpins,whichmusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasout-puts.Theseshouldbeplacedinaconditioninwhichminimumcurrentisdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSRev.1.10

33

August5,2011

HT82A836RNomatterwhatthesourceofthewake-upeventis,onceawake-upsituationoccurs,atimeperiodequalto1024systemclockperiodswillberequiredbeforenormalsys-temoperationresumes.However,ifthewake-uphasoriginatedduetoaninterrupt,theactualinterruptsub-routineexecutionwillbedelayedbyanadditionaloneormorecycles.Ifthewake-upresultsintheexecutionofthenextinstructionfollowingthe²HALT²instruction,thiswillbeexecutedimmediatelyafterthe1024systemclockperioddelayhasended.

sourceinsteadoftheinternalWDToscillator.Ifthein-structionclockisusedastheclocksource,itmustbenotedthatwhenthesystementersthePowerDownMode,asthesystemclockisstopped,thentheWDTclocksourcewillalsobestopped.ThereforetheWDTwillloseitsprotectingpurposes.Insuchcasesthesys-temcannotberestartedbytheWDTandcanonlybere-startedusingexternalsignals.Forsystemsthatoperateinnoisyenvironments,usingtheinternalWDToscillatoristhereforetherecommendedchoice.

Undernormalprogramoperation,aWDTtime-outwillinitialiseadeviceresetandsetthestatusbitTO.How-ever,ifthesystemisinthePowerDownMode,whenaWDTtime-outoccurs,onlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWDTandtheWDTprescaler.Thefirstisanexternalhardwarereset,whichmeansalowlevelontheRESETpin,thesecondisus-ingthewatchdogsoftwareinstructionsandthethirdisviaa²HALT²instruction.

TherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhichmustbechosenbyconfigurationoption.Thefirstoptionistousethesin-gle²CLRWDT²instructionwhilethesecondistousethetwocommands²CLRWDT1²and²CLRWDT2².Forthefirstoption,asimpleexecutionof²CLRWDT²willcleartheWDTwhileforthesecondoption,both²CLRWDT1²and²CLRWDT2²mustbothbeexecutedtosuccessfullycleartheWDT.Notethatforthissecondoption,if²CLRWDT1²isusedtocleartheWDT,succes-siveexecutionsofthisinstructionwillhavenoeffect,onlytheexecutionofa²CLRWDT2²instructionwillcleartheWDT.Similarly,afterthe²CLRWDT2²instruc-tionhasbeenexecuted,onlyasuccessive²CLRWDT1²instructioncancleartheWatchdogTimer.

WatchdogTimer

TheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlo-cations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.Itoperatesbyprovidingade-viceresetwhentheWDTcounteroverflows.TheWDTclockissuppliedbytwosourcesselectedbyconfigura-tionoption:itsownselfcontaineddedicatedinternalWDToscillatororfSYS/4.NotethatiftheWDTconfigura-tionoptionhasbeendisabled,thenanyinstructionrelat-ingtoitsoperationwillresultinnooperation.

TheinternalWDToscillatorhasanapproximateperiodof65msatasupplyvoltageof5V.Ifselected,itisfirstdi-videdby256viaan8-stagecounter.Notethatthispe-riodcanvarywithVDD,temperatureandprocessvariations.ForlongerWDTtime-outperiodstheWDTprescalercanbeutilized.Bywritingtherequiredvaluetobits0,1and2oftheWDTSregister,knownasWS0,WS1andWS2,longertime-outperiodscanbeachieved.WithWS0,WS1andWS2allequalto1,thedivisionratiois1:128whichgivesamaximumtime-outperiod.

Aconfigurationoptioncanselecttheinstructionclock,whichisthesystemclockdividedby4,astheWDTclock

WatchdogTimerRegister

Rev.1.1034August5,2011

HT82A836RWatchdogTimer

USBFunction

ThedeviceincludesaUSB1.1interfacewhichcanbeusedfordataapplicationdatatransfer.FiveendpointsareincludedintheUSBfunctionofthisdevice.USBInterface

TheInterfaceintheHT82A836Rdevicehas5End-points,knownasEP0~EP4.Endpoint0,EP0,isusedforControltransfer.EndpointsEP1andEP4areforInter-rupttransfer,whileEP2supportstheIsochronousouttransfer.EP3supportsIsochronousintransfer.AsetofregistersstoredintheDataMemoryisusedforoverallcontroloftheUSBfunction.Thesecontrolregistersin-clude,USC,USR,UCC,AWR,STALL,SIESandMISC.TherearealsofiveFIFOregisterswiththenamesFIFO0~FIFO4.ThesizeofeachFIFOisasfollows:,FIFO0-8bytes,FIFO1-8bytes,FIFO2-384bytes,FIFO3-32bytesandFIFO4-bytes,givingatotalof496bytes.TheURDbit,whichisbit7oftheUSCregisteristheUSBresetsignalcontrolfunctiondefinitionbit.USBInterfaceRegisters

TheUSBsetup,datamanagementandendpointcontrolinthedeviceiscontrolledviaaseriesofregistersintheDataMemory.USCRegister

TheUSCregisteristheregisterfortheoverallcontroloftheUSBfunction.Theinitialstatusofthisregisteris80H.

Furtherexplanationofeachofthebitsisgivenbelow:

·SUSP

·RMWK

TheRMWKread/writebitistheUSBremotewake-upcommand.ItissetbytheMCUtoallowtheUSBhosttoleavethesuspendmodeafteranexternalwake-up.

·URST

TheURSTread/writebitistheUSBresetindicationbit.ThisbitissetandclearedbytheUSBSIEandindi-catesaUSBreseteventontheUSBbus.Whenthisbitissetto²1²,thisindicatesthataUSBresethasoc-curredandthataUSBinterruptwillbegenerated.

·RESUME

TheRESUMEreadonlybitisusedtoindicatethattheUSBhaslefttheSuspendMode.WhentheUSBhaslefttheSuspendMode,thisread-onlybitissetto²1²bytheSIE.WhentheRESUMEbitissetbySIE,anin-terruptwillbegeneratedtowake-uptheMCU.Inordertodetectthesuspendstate,theMCUshouldsettheUSBCKENbitandclearSUSP2intheUCCregister,toenabletheSIEdetectfunction.TheRESUMEbitwillbeclearedwhenSUSPgoesto²0².WhentheMCUisdetectingtheSUSP,theconditionoftheRE-SUMEbit,whichwillwake-uptheMCU,shouldbenotedandtakenintoconsideration.

·V33C

TheV33Cread/writebitisthecontrolbitfortheinter-nallygenerated3.3VsupplyfortheUSBinterface.

·PLLENThePLLENread/writebitisthecontrolbitfortheinter-nalPhaseLockedLoopfunction.

·CRCFG

TheSUSPbitistheUSBSuspendIndicatorbit.Whenthisread-onlybitissetto²1²bytheSIE,itindicatesthattheUSBbushasenteredthesuspendmode.TheUSBinterruptisalsotriggeredwhenthisbitchangesfromlowtohigh.

TheCRCFGread/writebitistheCRCerrorconditionfailureflag.TheCRCFGbitwillbesetbythehardwarehowevertheCRCFGbitneedstobeclearedusingfirmware.

·URD

TheURDread/writebitistheUSBresetsignalcontrolfunctiondefinitionbit.

Rev.1.1035August5,2011

HT82A836RUSBControlRegister-USC

USRRegister

TheUSRregisteristheUSBendpointinterruptstatusregisterandisusedtoindicatewhichendpointisac-cessedandtoselecttheUSBbus.Theendpointrequestflags,EP0F,EP1F,EP2F,EP3FandEP4Fareusedtoindicatewhichendpointsareaccessed.Ifanendpointisaccessed,therelatedendpointrequestflagwillbesetto²1²andtheUSBinterruptwillbegeneratediftheUSBinterruptisenabledandthestackisnotfull.Whentheactiveendpointrequestflagisserviced,theendpointre-questflaghastobeclearedto²0²bysoftware.Furtherexplanationofeachofthebitsisgivenbelow:

·ESP0F~ESP4F

Furtherexplanationofeachofthebitsisgivenbelow:

·EPS0~EPS2

Thesethreeread/writebitsarefortheendpointFIFOselection.ItshouldbenotedthatIsochronousend-points2and3areimplementedinhardware,thereforeFIFO2andFIFO3cannotbereadfromorwrittentousingfirmware.

·USBCKEN

TheUSBCKENread/writebitenablestheUSBclock.

·SUSP2

TheSUSP2read/writebitisthesecondsuspendbitandisusedtoselectapowerreducingfunctionwhenthedeviceisintheSuspendMode.IntheNormalModethisbitshouldbeclearedtozero.

·FSYS16MHz

TheESP0F~ESP4Fread/writebitsaresetbytheSIEanindicatewhethertheassociatedendpointhasbeenaccessedandaUSBinterruptgenerated.Afterthein-terrupthasbeenservicedthebitsshouldbeclearedbytheapplicationprogram.UCCRegister

TheUCCregisteristhesystemclockcontrolregisterandisusedtoselecttheclockthatisusedintheMCU.ThisregisterconsistsofaUSBclockcontrolbit,USBCKEN,asecondsuspendmodecontrolbit,SUSP2,andasystemclockselectionbit,SYSCLK.Theregisteralsocontrolstheendpointselection,whichisdeterminedbybitsEPS0,EPS1andEPS2.

Thisread/writebitisusedtodetermineifthesystemclockisderivedfromanexternaloscillatororfromtheinternalPLL16MHzclock.

·SYSCLK

TheSYSCLKread/writebitisusedtodetermineifthesystemclockiseither6MHzor12MHz.AWRRegister

TheAWRregisterisusedtostorethecurrentUSBde-viceaddressandalsoforcontroloftheRemoteWake-upfunction.TheinitialvalueoftheAWRregisteris²00H².TheaddressvalueextractedfromtheUSBcommandmustnotbeloadedintothisregisteruntiltheSETUPstagehasfinished.

Rev.1.1036August5,2011

HT82A836RUSBEndpointStatusRegister-USR

SystemClockControlRegister-UCC

DeviceAddressRegister-AWR

Rev.1.1037August5,2011

HT82A836RSTALLRegister

TheSTALLregistershowswhetherthecorrespondingendpointhasoperatedcorrectlyornot.Assoonastheendpointhasoperatedincorrectly,therelatedread/writebitintheSTALLhastobesetto²1².TheSTALLregisterwillbeclearedbyaUSBresetsignalandasetuptokenevent.TheinitialvalueoftheSTALLregisteris²00H².SIESRegister

TheSIESregisteristhesetupregisterfortheSerialIn-terfaceEngine.

Furtherexplanationofeachofthebitsisgivenbelow:

·ASET

immediatelyafteranaddressiswrittentotheAWRregister.Thereforeinordertoworkproperly,thepro-gramhastoclearthisbitafteranextvalidSETUPto-kenisreceived.

·ERR

Theread/writeERRbitisusedtoindicatethaterrorshaveoccurredwhentheFIFOisaccessed.ThisbitissetbySIEandshouldbeclearedbytheprogram.Thisbitisusedforallendpoints.

·OUT

Theread/writeASETbitisusedtoconfiguretheSIEtoautomaticallychangethedeviceaddresstothevaluepresentlystoredintheAWRregister.Whenthisbitissetto²1²by,theSIEwillupdatethedeviceaddresswiththevaluestoredintheAWRregisterafterthePChosthassuccessfullyreadthedatafromthedevicewithanINoperation.Otherwise,whenthisbitisclearedto²0²,theSIEwillupdatethedeviceaddress

Theread/writeOUTbitisusedtoindicatetherecep-tionofanOUTtoken,exceptfortheOUTzerolengthtoken.ThedevicewillclearthisbitaftertheOUTdatahasbeenread.Also,thisbitwillbeclearedbytheSIEafterthenextvalidSETUPtokenisreceived.

·IN

ThereadonlyINbitisusedtoindicatethatthecurrentUSBreceivingsignalfromPChostisanINtoken.

·NAK

ThisreadonlybitisusedtoindicatethattheSIEhastransmittedaNAKsignaltothehostinresponsetothePChostINorOUTtoken.

EndpointStallRegister-STALL

SerialInterfaceSetupRegister-SIES

Rev.1.1038August5,2011

HT82A836R·CRCF

TheCRCFread/writeisanerrorconditionfailureflagthatincludesCRC,PIDandnointegratetokenerror.CRCFwillbesetbythehardwarebutneedstobeclearedbythefirmware.

·EOT

desirestowritedatatotheFIFO.Afterfinishing,thisbitmustbesetlowbeforeterminatingtherequesttorepresentatransitionend.ForanMCUreadopera-tion,thisbitmustbesetlowandthenhighafterfinish-ing.

·CLEAR

TheEOTreadonlyreadonlyflagistheTokenPack-ageactiveflag.Notethatthisflagisactivelow.

·NMI

Theread/writeNMIbitistheNAKtokeninterruptmaskflag.Ifthisbitset,whenthedevicesendsaNAKtokentothehost,theinterruptwillbedisabled.Other-wiseifthisbitiscleared,whenthedevicesendsaNAKtokentothehost,itwillentertheinterruptsub-routine.MISCRegister

TheMISCregistercombinescommandandstatustocontrolthedesiredendpointFIFOactionandtoshowthestatusofthedesiredendpointFIFO.TheMISCreg-isterwillbeclearedbyaUSBresetsignal.

Furtherexplanationofeachofthebitsisgivenbelow:

·REQUEST

Theread/writeCLEARbitMCUisusedtorequestaFIFOclear,eveniftheFIFOisnotready.AfterclearingtheFIFO,theUSBinterfacewillsendaforce_tx_errtotelltheHostthatdataunder-runiftheHostwantstoreaddata.

·ISO_IN_EN

Theread/writeISO_IN_ENbitenablestheisochronousinpipeinterrupt.

·ISO_OUT_EN

Theread/writeISO_OUT_ENbitenablestheisochronousoutpipeinterrupt.

·SETCMD

Theread/writeSETCMDbitisusedtoshowthatthedataintheFIFOisasetupcommand.Thebitwillre-maininthesamestateuntilthefollowingdataenterstheFIFO.

·READY

Theread/writeREQUEST,ifsethigh,canrequesttheFIFOafterthecorrespondingstatushasbeenset.Whenfinishedthisbitmustbesetlow.

·TX

ThereadonlyREADYbitisusedtoindicatethatthedesiredFIFOisready.

·LEN0

Theread/writeTXbitrepresentsthedirectionandMCUaccesstransitionend.Whensethigh,theMCU

ThereadonlyLEN0bitisusedtoindicatethatthehosthassenta0-sizedpackettotheMCU.ThisbitmustbeclearedbyareadactiontothecorrespondingFIFO.

MiscellaneousRegister-MISC

Rev.1.1039August5,2011

HT82A836RSETIORegister

TheSETIOregisterisusedtosetuptheendpointstoei-therinputoroutputpipetype.TheDATAtokentogglebitisalsocontainedwithinthisregister.NotethatforUSBdefinition,whenthehostsendsa²setConfiguration²,theDatapipeshouldsendDATA0,abouttheDatatog-gle,first.Therefore,whenthedevicereceivesa²setconfiguration²setupcommand,theuserneedstotogglethisbitasthefollowingdatawillsendDATA0first.Itisonlyrequiredtosetthedatapipeasaninputpileorout-putpile.ThepurposeofthisfunctionistoavoidthehostsendinganabnormalINorOUTtokenanddisablingtheendpoint.Allbitsareread/write.

SETIO(27H)register,USBEndpoint1~Endpoint4setIN/OUTpiperegister.USB_STATERegister

ThisregisterisusedtoindicatetheerrorstateduetoSE0orSE1noiseaswellastheUSBD-andUSBD+in-putsignals.TheSE0andSE1bitsaresetbytheSIEandclearedwiththeprogram.

SuspendWake-UpRemoteWake-Up

ThedeviceincludesaSuspendmode.Ifthereisnosig-nalontheUSBbusforover3ms,thedevicewillenterasuspendmode.Whenthishappens,theSUSPENDbit,whichisbit0oftheUSCregister,willbesetto²1²andaUSBinterruptwillbegeneratedtoindicatethatthede-viceshouldjumptothesuspendstatetomeetthere-quirementsoftheUSBsuspendcurrentspec.Inordertomeettherequirementsofthesuspendcurrent,thepro-gramshoulddisabletheUSBclockbyclearingtheUSBCKENbit,whichisbit3oftheUCCregister,to²0².Thesuspendcurrentcanbefurtherdecreasedbyset-tingtheSUSP2bit,whichisbit4oftheUCCregister.Whentheresumesignalissentoutbythehost,theHT82A836RwillbewokenupthebytheUSBinterruptandtheRESUMEbit,whichisbit3oftheUSCregister,willbeset.Inordertomakethedeviceoperatecorrectly,theprogrammustsettheUSBCKENbitandcleartheSUSP2bit.SincetheResumesignalwillbeclearedbe-foretheIdlesignalissentoutbythehostandtheSUS-PENDbit,willchangeto²0².ThereforewhentheMCUisdetectingtheSuspendline,theconditionoftheRe-sumelineshouldbenotedandtakenintoconsideration.

USBEndpointSetupIN/OUTPipeRegister-SETIO

USBStateRegister-USB-STATE

Rev.1.1040August5,2011

HT82A836RThefollowingshowstherelatedtimingofthisoperation:

Thefollowingshowstherelatedtiming:

Thedevicecontainsaremotewake-upfunctionwhichcanwake-uptheUSBHostbysendingawake-uppulsethroughtheRMWKbit,whichisbit1oftheUSCregister.OncetheUSBHostreceivesawake-upsignalfromthedevice,itwillsendaResumesignaltothedevice.

USBSpeakerVolumeControl

Thespeakeroutputvolumeaswellasthespeakermute/un-mutefunctionarecontrolledbytheUSBSpeakerVolumeControlUSVCregister.Thevolumerangecanbesetbetweenarangeof6dBto-32dBbysoftware.TherelationshipbetweentheUSVCvolumecontrolbitsandtheamplificationorattenuationvaluesareshownintheVolumeControlTa-ble.ThemutecontrolwillbeenabledwhentheMUTEbitislowandboththeDACandthepoweramplifierwillbemuted.

USBSpeakerVolumeControlRegister-USVC

Result(dB)65.554.543.532.521.510.50-0.5-1-1.5USVC000_1100000_1011000_1010000_1001000_1000000_0111000_0110000_0101000_0100000_0011000_0010000_0001000_0000111_1111111_1110111_1101Result(dB)-2-2.5-3-3.5-4-4.5-5-5.5-6-6.5-7-7.5-8-8.5-9-9.5USVC111_1100111_1011111_1010111_1001111_1000111_0111111_0110111_0101111_0100111_0011111_0010111_0001111_0000110_1111110_1110110_1101Result(dB)-10-10.5-11-11.5-12-13-14-15-16-17-18-19-20-21-22-23USVC110_1100110_1011110_1010110_1001110_1000110_0111110_0110110_0101110_0100110_0011110_0010110_0001110_0000101_1111101_1110101_1101Result(dB)-24-25-26-27-28-29-30-31-32¾¾¾¾¾¾¾USVC101_1100101_1011101_1010101_1001101_1000101_0111101_0110101_0101101_0100¾¾¾¾¾¾¾SpeakerVolumeControlTable

Rev.1.1041August5,2011

HT82A836RFIFORegistersRegistersFIFO0~FIFO4R/WR/WPower-onxxHFunctionEPiaccessingregister-EPSXbitsintheUCCregister.(i=0~4).Whenanend-pointisdisabled,thecorrespondingaccessingregistershouldbedisabled.FIFO0~FIFO4(28H~2CH)USBEndpointAccessingRegistersDefinitions

DACLimitRegisters

TheDAC_Limit_LandDAC_Limit_Hregistersareusedtodefinethe16-bitDACoutputlimits.ThevaluesintheDAC_Limit_LandDAC_Limit_Hregistersareunsignedvalues.Ifthe16-bitdatafromtheHostexceedsthatoftherangedefinedbythetwoDAC_Limit_LandDAC_Limit_HregistersthentheoutputdigitalcodetoDACwillbeclampedwithintheseregistervalues.

DAC_Limit_LDAC_Limit_H

DACoutputlimitlowbyteDACoutputlimithighbyte

ExampletosettheDACoutputlimitvalues:

;-----------------------------------------------------------;SetDACLimitValue=FF00H

;-----------------------------------------------------------clr[02DH];SetDACLimitlowbyte=00Hset[02EH];SetDACLimithighbyte=FFH

;-----------------------------------------------------------Inordertopreventapoppingnoisefromthespeakeroutput,thepoweramplifiershouldoutputavalueofVDD/2,whichmeansavalueof8000HshouldbesenttotheDACduringtheinitialpoweronstate.GeneratingapulseontheDAC_WR_TRIGbitwillwritethevaluesintotheDAC.IftheDAC_WR_TRIG,bit3oftheDAC_WRregister,isalreadyhighthenclearingtheDAC_WR_TRIGbit,willwritethevaluesintotheDAC_Limit_LandDAC_Limit_HregistersfortheDAC.

DACWriteandRecordSourceRegister-DAC_WR

Note:

IntheDACwritedatamode(highnibbleofWDTSregisteris0101b),theDAC_Limit_LandDAC_Limit_Hreg-isterswillbethe16-bitDACinputdataregisteratthefallingedgeofDAC_WR_TRIG.Otherwise,thesetworegistersareusedtodefinethe16-bitDACoutputlimit(repeatedbelow).

Rev.1.1042August5,2011

HT82A836RREC_MODE=1:WritingtoRECORD_IN_Lregisterwillonlyputthewrittendatatoaninternallower-orderbytebuffer(8-bit)andwritingRECORD_IN_HwilltransfertheRECORD_IN_LandRECORD_IN_Hregisterscontenttoisochronousinbuffer.Whenrecordinterrupthappened,firmwareshouldwrite16-bit2¢scomplementvaluetoRE-CORD_IN_LandRECORD_IN_H(RECORD_U_EN=0)registersorwrite8-bitmlawvaluetoRECORD_IN_Hregister(RECORD_U_EN=1).REC_MODE=²1²REC_MODE=²0²

RecorddatacomesfromtheRECORD_IN_HandRECORD_IN_LregistersRecorddatacomesfromthePCMADC(Default=0)

TherecordwritedataformatwillbecontrolledbybitRECORD_U_ENofOPER_MODEregisterwhenREC_MODE=²1².

Therecorddatawriteformatasfollow:

RECORD_IN_LRECORD_U_EN=0RECORD_U_EN=1PCM(Lowbyte)N/ARECORD_IN_HPCM(Highbyte)mLawExampleProgramtoEliminatePopNoise:System_Initial:

;-----------------------------------------------------------;AvoidPopNoise

;-----------------------------------------------------------mova,WDTS

movFIFO_TEMP,a;SaveWDTSvaluemova,00001111bmova,WDTS

mova,01010000borma,WDTS;EnterDACWriteDatamode,highnibbleofWDTS=0101bclr[02DH];SetDACdatalowbyte=00Hmova,80Hmov[02EH],a;SetDACdatahighbyte=80H;Write8000HtoDACset[02FH].3clr[02FH].3

;-----------------------------------------------------------mova,FIFO_TEMP;RestoreWDTSvaluemovWDTS,a;QuitDACWriteDatamode

;-----------------------------------------------------------

Rev.1.1043August5,2011

HT82A836RDigitalProgrammableGainAmplifier-PGA

ThedeviceincludesafullyintegratedProgrammableGainAmplifier,otherwiseknownasthePGA.ThePGAisadigitalamplifierusedtoamplifythe16-bitdatathatcomesfromthePCMA/DConverter(REC_MODE(2FH.0)=0)orfromtheRECORD_IN_HandRE-CORD_IN_L(REC_MODE(2FH.0)=1).

ThePGAfunctioniscontrolledusingthePGA_CTRLregisterwithinwhichthereissixbitstocontrolthegainvalue.Thisgainvaluerangesfrom0dBuptoamaxi-mumof19.5dB,instepsof0.5dB,andisselectedusingthePGA0~PGA5bits.

PGABlockDiagram

ProgrammableGainAmplifierControlRegister-PGA_CTRL

Rev.1.1044August5,2011

HT82A836RSPISerialInterface

ThedeviceincludesasingleSPISerialInterface.TheSPIinterfaceisafullduplexserialdatalink,originallydesignedbyMotorola,whichallowsmultipledevicesconnectedtothesameSPIbustocommunicatewitheachother.Thedevicescommunicateusingamas-ter/slavetechniquewhereonlythesinglemasterdevicecaninitiateadatatransfer.Asimplefourlinesignalbusisusedforallcommunication.SPIInterfaceCommunication

FourlinesareusedforSPIcommunicationknownasSDI-SerialDataInput,SDO-SerialDataOutput,SCK-SerialClockandSCS-SlaveSelect.NotethattheconditionoftheSlaveSelectlineisconditionedbytheCSENbitintheSBCRcontrolregister.IftheCSENbitishighthentheSCSlineisactivewhileifthebitislowthentheSCSlinewillbeinafloatingcondition.ThefollowingtimingdiagramdepictsthebasictimingprotocoloftheSPIbus.SPIRegisters

TherearetworegistersassociatedwiththeSPIInter-face.ThesearetheSBCRregisterwhichisthecontrolregisterandtheSBDRwhichisthedataregister.TheSBCRregisterisusedtosetuptherequiredsetuppa-rametersfortheSPIbusandalsousedtostoreassoci-atedoperatingflags,whiletheSBDRregisterisusedfordatastorage.

AfterPoweron,thecontentsoftheSBDRregisterwillbeinanunknownconditionwhiletheSBCRregisterwillde-faulttotheconditionbelow:CKS0M11M0SBENMLSCSENWCOLTRF100000NotethatdatawrittentotheSBDRregisterwillonlybewrittentotheTXRXbuffer,whereasdatareadfromtheSBDRregisterwillactuallybereadfromtheregister.SPIBusEnable/Disable

ToenabletheSPIbusthenCSEN=1andSBEN=1,theSCK,SDI,SDOandSCSlinesshouldallbezero,thenwaitfordatatobewrittentotheSBDR(TXRXbuffer)register.FortheMasterMode,afterdatahasbeenwrit-tentotheSBDR(TXRXbuffer)registerthentransmis-sionorreceptionwillstartautomatically.WhenallthedatahasbeentransferredtheTRFbitshouldbeset.FortheSlaveMode,whenclockpulsesarereceivedonSCK,dataintheTXRXbufferwillbeshiftedoutordataonSDIwillbeshiftedin.

ToDisabletheSPIbusSCK,SDI,SDO,SCSfloating.SPIOperationAllcommunicationiscarriedoutusingthe4-lineinter-faceforbothMasterorSlaveMode.Thetimingdiagramshowsthebasicoperationofthebus.SPIBlockDiagram

Rev.1.1045August5,2011

HT82A836RSPIInterfaceControlRegister

SPIBusTiming

TheSBENbitdeterminesifpinsPC4~PC7areusedasnormalI/OpinsorasSPIfunctionpins.IfthisbitishighthenthepinswillbeSPIfunctionpinsandherepinSCSwillgolowifCSEN=1.IfthebitislowthenthepinswillfunctionasnormalI/Opins.NotethatwhenSBEN=1,thenanypull-highresistorsconnectedtopinsPC4~PC7willbedisconnectedthereforetheuserhardwareshouldensurethatexternalpull-highresistorsareaddedtotheSPIpinsifnecessary.IfCSEN=0thentheSCSpinwillbeinafloatingstate.

TheSPIclockpolarityiscontrolledusingtheSIO_CPOLbitintheMODE_CTRLregister.IfSIO_CPOL=1,thentherisingedgewillbeselected.OtherwiseifSIO_CPOL=0,thefallingedgewillbeselected.

TheCSENbitintheSBCRregistercontrolstheoverallfunctionoftheSPIinterface.Settingthisbithigh,willen-abletheSPIinterfacebyallowingtheSCSlinetobeac-tive,whichcanthenbeusedtocontroltheSPIinterface.IftheCSENbitislow,theSPIinterfacewillbedisabledandtheSCSlinewillbeinafloatingconditionandcanthereforenotbeusedforcontroloftheSPIinterface.TheSBENbitintheSBCRregistermustalsobehighwhichwillchangethepinfunctionfromastandardI/OtoanSPIfunctionpin.IfintheMasterModetheSCKlinewillbeeitherhighorlowdependingupontheclockpo-larityconfigurationoption.IfintheSlaveModetheSCKlinewillbeinafloatingcondition.IfSBENislowthenthebuswillbedisabled.

Rev.1.1046August5,2011

HT82A836RIntheMasterModetheMasterwillalwaysgeneratetheclocksignal.Theclockanddatatransmissionwillbeini-tiatedafterdatahasbeenwrittentotheSBDRregister.IntheSlaveMode,theclocksignalwillbereceivedfromanexternalmasterdeviceforbothdatatransmissionorreception.ThefollowingsequencesshowtheordertobefollowedfordatatransferinbothMasterandSlaveMode:

·MasterMode:

Step1.SelecttheclocksourceusingtheCKSbitin

theSBCRcontrolregister.Step2.SetuptheM0andM1bitsintheSBCRcontrol

registertoselecttheMasterModeandtherequiredBaudrate.Valuesof00,01or10canbeselected.Step3.SetuptheCSENbitandsetuptheMLSbitto

chooseifthedataisMSBorLSBfirst,thismustbesameastheSlavedevice.Step4.SetuptheSBENbitintheSBCRcontrol

registertoenabletheSPIinterface.

·Step5.Forwriteoperations:writethedatatothe

theTXRXregister,thenwaitforthemasterclockandSCSsignal.Afterthisgotostep6.Forreadoperations:thedatatransferredinontheSDIlinewillbestoredintheTXRXbufferuntilallthedatahasbeenreceivedatwhichpointitwillbelatchedintotheSBDRregister.

Step6.ChecktheWCOLbit,ifsethighthena

collisionerrorhasoccurredsoreturntostep5.Ifequaltozerothengotothefollowingstep.

Step7.ChecktheTRFbitorwaitforanSBIserialbus

interrupt.

Step8.ReaddatafromtheSBDRregister.Step9.ClearTRFStep10.Gotostep5SBEN=²1²SBEN=²0²Note:

PC4~PC7areSPIfunctionpins(pinSCSwillgolowifCSEN=1).PC4~PC7aregeneralpurposeI/OPortpins(Default)

SBDRregister,whichwillactuallyplacethedataintotheTXRXbuffer.ThenusetheSCKandSCSlinestooutputthedata.Afterthisgototostep6.

Forreadoperations:thedatatransferredinontheSDIlinewillbestoredintheTXRXbufferuntilallthedatahasbeenreceivedatwhichpointitwillbelatchedintotheSBDRregister.

Step6.ChecktheWCOLbit,ifsethighthena

collisionerrorhasoccurredsoreturntostep5.Ifequaltozerothengotothefollowingstep.Step7.ChecktheTRFbitorwaitforanSBIserialbus

interrupt.Step8.ReaddatafromtheSBDRregister.Step9.ClearTRF.Step10.Gotostep5.

·SlaveMode:

(1)IfSBEN=²1²,thepull-highresistorofPC4~PC7willbedisable.Whenthishappens,theusershouldaddexternalpull-highresistorstotheSPIrelatedpinsifnecessary(EX:pinSCS).(2)IfCSEN=²0²,theSCSpinwillenterafloat-ingstate.

TheSPIcockpolaritycontrolledbySIO_CPOLbitofMODE_CTRLregister.IfSIO_CPOL=²1²,risingedge(CLK)willbeselected.OtherwiseSIO_CPOL=²0²,fall-ingedge(CLK)willbeselected.ErrorDetection

TheWCOLbitintheSBCRregisterisprovidedtoindi-cateerrorsduringdatatransfer.ThebitissetbytheSe-rialInterfacebutmustbeclearedbytheapplicationprogram.ThisbitindicatesadatacollisionhasoccurredwhichhappensifawritetotheSBDRregistertakesplaceduringadatatransferoperationandwillpreventthewriteoperationfromcontinuing.ThebitwillbesethighbytheSerialInterfacebuthastobeclearedbytheuserapplicationprogram.TheoverallfunctionoftheWCOLbitcanbedisabledorenabledbyaSIO_WCOLbitofMODE_CTRLregister.ProgrammingConsiderations

WhenthedeviceisplacedintothePowerDownModenotethatdatareceptionandtransmissionwillcontinue.TheTRFbitisusedtogenerateaninterruptwhenthedatahasbeentransferredorreceived.

Step1.TheCKSbithasadon¢tcarevalueinthe

slavemode.

Step2.SetuptheM0andM1bitsto00toselectthe

SlaveMode.TheCKSbitisdon¢tcare.

Step3.SetuptheCSENbitandsetuptheMLSbitto

chooseifthedataisMSBorLSBfirst,thismustbesameastheMasterdevice.

Step4.SetuptheSBENbitintheSBCRcontrol

registertoenabletheSPIinterface.

Step5.Forwriteoperations:writedatatotheSBCR

register,whichwillactuallyplacethedatainto

Rev.1.1047August5,2011

HT82A836RModeControlRegister

TheMODE_CTRLregisterisusedtocontrolDACandADCoperationmodeandSPIfunction.NotethattheWCOLandCSENbitsareintheSBCRregister.SPIusageexample:SPI_Test:

clrUCC.@UCC_SYSCLK

setSIO_CSEN

clrSIO_CPOL

;MasterMode,SCLK=fSIOclrM1clrM0;--------------clrCKSclrTRFclrTRF_INTsetMLSsetCSENsetSBEN

ifPOLLING_MODE

clrESII

;WRITEINTO²WRITEENABLE²INSTRUCTION

MOVA,OP_WRENMOVSBDR,A

$0:

snzTRFjmp$0clrTRF

else

setESII

;WRITEINTO²WRITEENABLE²INSTRUCTION

MOVA,OP_WRENMOVSBDR,A

$0:

snzTRF_INTjmp$0clrTRF_INT

endif

;12MHzSYSCLK

;SPIChipSelectFunctionEnable;fallingedgechangedata

;fSIO=fSYS/2

;clearTRFflag

;clearInterruptSPIflag;MSBshiftfirst;ChipSelectEnable

;SPIEnable,SCSwillgolow;SPIInterruptDisable

;SPIInterruptEnable

;setatSPIInterrupt

ModeControlRegister-MODE_CTRL

Rev.1.1048August5,2011

HT82A836ROperationModeControlRegister

TheOPER_MODEregisterisusedtocontrolcertainoperationaloperationalmodes.Theoperationmodeisusedtocontrolthemlawcompanderenable/disableforthespeakerandmicrophonedata.

OperationModeControlRegister-OPER_MODE

Play/RecordData

ThePlayandRecorddataforthedeviceiscontainedin4Playregistersand2Recordregisters.Theplay/recordinter-ruptwillbeactivatedwhenplay/recorddatainthePLAY_DATAorRECORD_DATAregistersisvalid.ThePLAY_DATA/RECORD_DATAregisterswilllatchdatauntilthenextinterruptisgenerated.TheDACPLAY_DATAreg-istercontainsanunsignedvaluewitharangeof0~FFFFH.TheRECORD_DATAisstoredin2¢scomplementformatwitharangeof8000H~7FFFH.

TheupdaterateofthePCMADCRECORD_DATAis8kHzwiththeRecord_FreqbitintheMODE_CTRLregisterisequalto0,or16kHzifthebitissetto1.TheupdaterateforthePLAY_DATAis48kHz,ifthePLAY_MODEbitintheMODE_CTRLregisterisequalto0,or8kHzifthebitisequalto1.AllofthePLAYandRECORDregistersarereadonly.

NamePLAY_DATAL_LPLAY_DATAL_HPLAY_DATAR_LPLAY_DATAR_HRECORD_DATA_LRECORD_DATA_Hb7PL_D7PL_D15PR_D7PR_D15R_D7R_D15b6PL_D6PL_D14PR_D6PR_D14R_D6R_D14b5PL_D5PL_D13PR_D5PR_D13R_D5R_D13b4PL_D4PL_D12PR_D4PR_D12R_D4R_D12b3PL_D3PL_D11PR_D3PR_D11R_D3R_D11b2PL_D2PL_D10PR_D2PR_D10R_D2R_D10b1PL_D1PL_D9PR_D1PR_D9R_D1R_D9b0PL_D0PL_D8PR_D0PR_D8R_D0R_D8TheplaydataformatiscontrolledbybitPLAY_U_ENintheOPER_MODEregister.

PLAY_DATAL_LPLAY_U_EN=0PLAY_U_EN=1PCM(LeftChannelLowByte)N/APLAY_DATAL_HPCM(LeftChannelHighByte)mLaw(LeftChannel)PLAY_DATAR_LPCM(RightChannelLowByte)N/APLAY_DATAR_HPCM(RightChannelHighByte)mLaw(RightChannel)TherecorddataregistersRECORD_DATA_L/RECORD_DATA_HwillnotbeaffectedbybitRECORD_U_ENintheOPER_MODEregister.TherecorddataregistersRECORD_DATA_L/RECORD_DATA_HareinPCMformat.

Rev.1.1049August5,2011

HT82A836RPulseWidthModulator

Thedevicecontainsa2channelPulseWidthModulatorfunction,morecommonlyknownasPWM.Usefulforsuchapplicationssuchasmotorspeedcontrol,thePWMfunctionprovidesoutputswithafixedfrequencybutwithadutycyclethatcanbevariedbysettingpartic-ularvaluesintothecorrespondingPWMregisters.ThedevicehastwoPWMoutputsforwhichtwo8-bitPWMregistersareprovidedandareknownasPWM0andPWM1.Itisintheseregisters,thatthe8-bitvalue,whichrepresentstheoveralldutycycleofonemodula-tioncycleoftheoutputwaveform,shouldbeplaced.ToincreasethePWMmodulationfrequency,eachmodula-tioncycleismodulatedintotwoorfourindividualmodu-lationsub-sections,knownasthe7+1modeor6+2respectively.ThemodeselectionismadeusingthePWMCregister.NotethatitisonlynecessarytowritetherequiredmodulationvalueintothecorrespondingPWM0orPWM1register,asthesubdivisionofthewaveformintoitssub-modulationcyclesisimplementedautomaticallywithinthemicrocontrollerhardware.Foralldevices,thePWMclocksourceisthesystemclockfSYS.

Thismethodofdividingtheoriginalmodulationcycleintoafurther2or4sub-cyclesenablesthegenerationofhigherPWMfrequencies,whichallowawiderrangeofapplicationstobeserved.AslongastheperiodsofthegeneratedPWMpulsesarelessthanthetimeconstantsoftheload,thePWMoutputwillbesuitablefordriving,assuchlongtimeconstantloadswillaverageoutthepulsesofthePWMoutput.ThedifferencebetweenwhatisknownasthePWMcyclefrequencyandthePWMmodulationfrequencyshouldbeunderstood.AsthePWMclockisthesystemclock,fSYS,andasthePWMvalueis8-bitswide,theoverallPWMcyclefrequencyisfSYS/256.Howeverwheninthe7+1modeofoperation,thePWMmodulationfrequencywillbefSYS/128,whilethePWMmodulationfrequencyforthe6+2modeofop-erationwillbefSYS/.

TheoverallPWMoutputenable/disableiscontrolledus-ingthePWMCregisterwhichactslikeanon/offswitchforeachPWMoutput.

PWMModulationfSYS/for(6+2)bitsmodefSYS/128for(7+1)bitsmode6+2PWMMode

EachfullPWMcycle,asitiscontrolledbyan8-bitPWMregister,has256clockperiods.However,inthe6+2PWMmode,eachPWMcycleissubdividedintofourin-dividualsub-cyclesknownasmodulationcycle0~mod-ulationcycle3,denotedasiinthetable.Eachoneofthesefoursub-cyclescontainsclockcycles.Inthismode,amodulationfrequencyincreaseoffourisachieved.The8-bitPWMregistervalue,whichrepre-sentstheoveralldutycycleofthePWMwaveform,isdi-videdintotwogroups.Thefirstgroupwhichconsistsofbit2~bit7isdenotedhereastheDCvalue.Thesecondgroupwhichconsistsofbit0~bit1isknownastheACvalue.Inthe6+2PWMmode,thedutycyclevalueofeachofthefourmodulationsub-cyclesisshowninthefollowingtable.

ParameterAC(0~3)iThefollowingdiagramillustratesthewaveformsassoci-atedwiththe6+2modeofPWMoperation.Itisimpor-tanttonotehowthesinglePWMcycleissubdividedinto4individualmodulationcycles,numberedfrom0~3andhowtheACvalueisrelatedtothePWMvalue.

(6+2)PWMModeOutputWaveform

Rev.1.10

50

August5,2011

HT82A836RPulseWidthModulationRegistersfor(6+2)PWMMode

7+1PWMMode

EachfullPWMcycle,asitiscontrolledbyan8-bitPWMregister,has256clockperiods.However,inthe7+1PWMmode,eachPWMcycleissubdividedintotwoindi-vidualsub-cyclesknownasmodulationcycle0~modula-tioncycle1,denotedasiinthetable.Eachoneofthesetwosub-cyclescontains128clockcycles.Inthismode,amodulationfrequencyincreaseoftwoisachieved.The8-bitPWMregistervalue,whichrepresentstheoveralldutycycleofthePWMwaveform,isdividedintotwogroups.Thefirstgroupwhichconsistsofbit1~bit7isde-notedhereastheDCvalue.Thesecondgroupwhichconsistsofbit0isknownastheACvalue.Inthe7+1PWMmode,thedutycyclevalueofeachofthetwomod-ulationsub-cyclesisshowninthefollowingtable.

ParameterAC(0~1)iThefollowingdiagramillustratesthewaveformsassoci-atedwiththe7+1modeofPWMoperation.Itisimpor-tanttonotehowthesinglePWMcycleissubdividedinto2individualmodulationcycles,numberedfrom0~1andhowtheACvalueisrelatedtothePWMvalueinthe7+1PWMMode.

(7+1)PWMModeOutputWaveform

PulseWidthModulationRegistersfor(7+1)PWMMode

Rev.1.1051August5,2011

HT82A836RPWMOutputControl

ControlofthetwoPWMoutputsisachievedusingthePWMCregister.Bitswithinthisregistercontroltheon/offfunctionoftheindividualPWMoutputsaswellastheirchosenmodetype.NotethanwhenthePWMoutputsaredisabledtheywillremaininalowstate.

PWMControlRegister-PWMC

PWMProgrammingExample

ThefollowingsampleprogramshowshowthePWMoutputsaresetupandcontrolled.BeforeusethecorrespondingPWMoutputconfigurationoptionsmustfirstbeselected.movmovclrset::clr

a,hPWM0,a

PWMC.PWM_MOD0PWMC.PWM_EN0

;setupPWM0valueof100decimalwhichisH;setuppinPWM0tothe6+2PWMMode;enablePWM0output

PWMC.PWM_EN0;disablePWM0output

Rev.1.1052August5,2011

HT82A836RAnalogtoDigitalConverter

Theneedtointerfacetorealworldanalogsignalsisacommonrequirementformanyelectronicsystems.However,toproperlyprocessthesesignalsbyamicrocontroller,theymustfirstbeconvertedintodigitalsignalsbyA/Dconverters.ByintegratingtheA/Dcon-versionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.A/DOverview

Thedevicecontainsa6-channelanalogtodigitalcon-verterwhichcandirectlyinterfacetoexternalanalogsig-nals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.

Thefollowingdiagramshowstheoverallinternalstruc-tureoftheA/Dconverter,togetherwithitsassociatedregisters.

A/DConverterDataRegisters-ADRL,ADRHFortheHT82A836Rdevice,whichhasa12-bitA/Dcon-verter,tworegistersarerequired,ahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL,tostorethe12-bitanalogtodigitalconversionvalue.Aftertheconversionprocesstakesplace,theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.NotethatonlythehighbyteregisterADRHutilisesitsfull8-bitcontents.Thelowbyteregisterutilisesonly4bitsofits8-bitcon-tentsasitcontainsonlythelowestbitofthe12-bitcon-vertedvalue.

Inthefollowingtables,D0~D11aretheA/Dconversiondataresultbits.

RegisterBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0ADRLADRHD3D2D1D0D8¾D7¾D6¾D5¾D4D11D10D9A/DConverterDataRegister

A/DConverterControlRegister-ADCR

TocontrolthefunctionandoperationoftheA/Dcon-verter,acontrolregisterknownasADCRisprovided.This8-bitregisterdefinesfunctionssuchastheselec-tionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,poweron/offtheA/Dconverter,controlthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.

OnesectionofthisregistercontainsthebitsACS2~ACS0whichdefinethechannelnumber.Aseachofthedevicescontainsonlyoneactualanalogtodigitalconvertercircuit,eachoftheindividual6analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS2~ACS0bitsintheADCRregistertodeterminewhichanalogchannelisactuallyconnectedtotheinter-nalA/Dconverter.

TheADCRcontrolregisteralsocontainsthePCR2~PCR0bitswhichdeterminepoweron/offtheA/Dconverterand.IfthePCR2~PCR0bitsareallsettozero,thentheinternalA/Dconvertercircuitrywillbepoweredofftoreducethepowerconsumption.Anyothernon-zerocombinationonthePCR2~PCR0bitswillpower-onthetheA/Dconverterwillbepoweronwhichwillconsumeacertainamountofpower.

A/DConverterStructure

Rev.1.1053August5,2011

HT82A836RTheSTARTbitintheADCRregisterisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theEOCBbitintheADCRregisterwillbesettoa²1²andtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallon/offopera-tionoftheinternalanalogtodigitalconverter.

TheEOCBbitintheADCRregisterisusedtoindicatewhentheanalogtodigitalconversionprocessiscom-plete.Thisbitwillbeautomaticallysetto²0²bythemicrocontrollerafteraconversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinter-ruptsareenabled,anappropriateinternalinterruptsig-nalwillbegenerated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/Dinter-nalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCRregistertocheckwhetherithasbeenclearedasanalternativemethodofdetect-ingtheendofanA/Dconversioncycle.

A/DConverterClockSourceRegister-ACSRTheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,isfirstdividedbyadivisionratio,thevalueofwhichisdeterminedbytheADCS1andADCS0bitsintheACSRregister.

AlthoughtheA/Dclocksourceisdeterminedbythesys-temclockfSYS,andbybitsADCS1andADCS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.A/DInputPins

AlloftheA/DanaloginputpinsareindependentanaloginputsandnotsharedwithotherI/Opins.BitsPCR2~PCR0intheADCRregister,notconfigurationoptions,determinewhethertheA/Dconverterispow-eredonorpowereddown.TheAVDD4powersupplypinisusedastheA/Dconverterreferencevoltage,andassuchanaloginputsmustnotbeallowedtoexceedthisvalue.AppropriatemeasuresshouldalsobetakentoensurethattheAVDD4pinremainsasstableandnoisefreeaspossible.

ADCRRegister

A/DConverterClockSourceRegister

Rev.1.10

54

August5,2011

HT82A836RInitialisingtheA/DConverter

TheinternalA/Dconvertermustbeinitialisedinaspe-cialway.EachtimetheA/Dchannelselectionbitsaremodifiedbytheprogram,theA/Dconvertermustbere-initialised.IftheA/Dconverterisnotinitialisedafterthechannelselectionbitsarechanged,theEOCBflagmayhaveanundefinedvalue,whichmayproduceafalseendofconversionsignal.ToinitialisetheA/Dcon-verterafterthechannelselectionbitshavechanged,then,withinatimeframeofonetoteninstructioncycles,theSTARTbitintheADCRregistermustfirstbesethighandthenimmediatelyclearedtozero.ThiswillensurethattheEOCBflagiscorrectlysettoahighcondition.SummaryofA/DConversionSteps

ThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dcon-versionprocess.

·Step1

A/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,intheINTC0interruptcontrolregistermustbesetto²1²,themulti-function1inter-ruptcontrolbit,EMF1I,intheINTC1registerandtheA/Dconverterinterruptbit,EADI,intheMFI1Cregis-termustalsobesetto²1².

·Step5

TheanalogtodigitalconversionprocesscannowbeinitialisedbysettingtheSTARTbitintheADCRregis-terfrom²0²to²1²andthento²0²again.Notethatthisbitshouldhavebeenoriginallysetto²0².

·Step6

Tocheckwhentheanalogtodigitalconversionpro-cessiscomplete,theEOCBbitintheADCRregistercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethodifthein-terruptsareenabledandthestackisnotfull,thepro-gramcanwaitforanA/Dinterrupttooccur.

Note:Whencheckingfortheendoftheconversion

process,ifthemethodofpollingtheEOCBbitintheADCRregisterisused,theinterruptenablestepabovecanbeomitted.Thefollowingtimingdiagramshowsgraphicallythevari-ousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.

ThesettingupandoperationoftheA/Dconverterfunc-tionisfullyunderthecontroloftheapplicationprogramastherearenoconfigurationoptionsassociatedwiththeA/Dconverter.AfteranA/Dconversionprocesshasbeeninitiatedbytheapplicationprogram,themicrocontrollerinternalhardwarewillbegintocarryouttheconversion,duringwhichtimetheprogramcancon-tinuewithotherfunctions.

SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCS1andADCS0intheACSRregister.

·Step2

SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS2~ACS0bitswhicharealsocontainedintheADCRregister.

·Step3

SelectA/Dconverterpoweronorpowerdownbypro-grammingthePCR2~PCR0bitsintheADCRregister.NotethatthisstepcanbecombinedwithStep2intoasingleADCRregisterprogrammingoperation.

·Step4

Iftheinterruptsaretobeused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensurethe

A/DConversionTiming

Rev.1.1055August5,2011

HT82A836RProgrammingConsiderations

Whenprogramming,specialattentionmustbegiventotheA/DchannelselectionbitsintheADCRregister.ThisabilitytoreducepowerbyturningofftheinternalA/DfunctionbyclearingtheA/Dchannelselectionbitsmaybeanimportantconsiderationinbatterypoweredappli-cations.

AnotherimportantprogrammingconsiderationisthatwhentheA/DchannelselectionbitschangevaluetheA/Dconvertermustbere-initialised.ThisisachievedbypulsingtheSTARTbitintheADCRregisterimmediatelyafterthechannelselectionbitshavechangedstate.

Theexceptiontothisiswherethechannelselectionbitsareallcleared,inwhichcasetheA/Dconverterisnotre-quiredtobere-initialised.A/DProgrammingExample

ThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample,themethodofpollingtheEOCBbitintheADCRregisterisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example:usinganEOCBpollingmethodtodetecttheendofconversionfortheHT82A836R.

clrEADI;disableADCinterruptmova,00000001BmovACSR,a;setuptheACSRregistertoselectfSYS/8astheA/D

;clock

mova,00100000B;setuptheADCRregistertopoweruptheA/D

;converter

movADCR,a;andselectAN0tobeconnectedtotheA/D

;converter

:;thefollowingSTARTsignal(0-1-0)mustbeissued:;within10instructioncycles:

Start_conversion:

clrSTARTSetSTART;resetA/DclrSTART;startA/D

Polling_EOC:

szEOCB;polltheADCRregisterEOCBbittodetectend

;ofA/Dconversion

jmppolling_EOC;continuepollingmova,ADRH;readconversionresulthighbytevaluefromthe

;ADRHregister

Adr_buffer_h,a;saveresulttouserdefinedmemorymova,ADRL;readconversionresultlowbytevaluefromthe

;ADRLregister

movadr_buffer_l,a;saveresulttouserdefinedmemory

::

jmpstart_conversion;startnextA/Dconversion

Rev.1.1056August5,2011

HT82A836RExample:usinganinterruptmethodtodetecttheendofconversionfortheHT82A836R.

clrEADI;disableADCinterruptmova,00000001BmovACSR,a;setuptheACSRregistertoselectfSYS/8astheA/D

;clock

mova,00100000B;setuptheADCRregistertopoweruptheA/D

;converter

movADCR,a;andselectAN0tobeconnectedtotheA/D

;converter

:;thefollowingSTARTsignal(0-1-0)mustbeissued::

Start_conversion:

clrADFsetEMF1IsetEADIsetEMIclrSTARTsetSTARTclrSTART

:::

;ADCinterruptserviceroutineADC_ISR:

clrADF

movacc_stack,amova,STATUS

movstatus_stack,a

::

mova,ADRH

movadr_buffer_h,amova,ADRL

movadr_buffer_l,a

::

EXIT_INT_ISR:

mova,status_stackmovSTATUS,amova,acc_stackreti

;within10instructioncycles

;;;;clearADCinterruptrequestflagMultifunction1interruptEnableenableADCinterruptenableglobalinterrupt

;resetA/D;startA/D

;clearADCinterruptrequestflag;saveACCtouserdefinedmemory;saveSTATUStouserdefinedmemory

;;;;;;readADRHsavereadADRLsaveconversionresulthighbytevaluefromtheregister

resulttouserdefinedregister

conversionresultlowbytevaluefromtheregister

resulttouserdefinedregister

;restoreSTATUSfromuserdefinedmemory;restoreACCfromuserdefinedmemory

Rev.1.1057August5,2011

HT82A836RA/DTransferFunction

AstheHT82A836Rdevicecontainsa12-bitA/Dconverter,theirfull-scaleconverteddigitisedvalueisequaltoFFFH.Sincethefull-scaleanaloginputvalueisequaltothevoltage,thisgivesasinglebitanaloginputvalueofVDD/4096.ThefollowinggraphsshowtheidealtransferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefortheA/Dconverters.Notethattoreducethequantisationerror,a0.5LSBoffsetisaddedtotheA/DConverterinput.Exceptforthedigitisedzerovalue,thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDlevel.

IdealA/DTransferFunction

Rev.1.1058August5,2011

HT82A836RConfigurationOptions

ConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintotheOTPProgramMemoryde-viceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopmenttools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,oncetheyareselectedtheycannotbechangedlaterbytheapplicationsoftware.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.No.I/OOptions1234567PA0~PA7:pull-highenableordisable(bitoption)PB0~PB7:pull-highenableordisable(bitoption)PC0~PC7:pull-highenableordisable(nibbleoption)PD0~PD7:pull-highenableordisable(bitoption)PE0~PE7:pull-highenableordisable(bitoption)PF0~PF3:pull-highenableordisable(bitoption)PA0~PA7:wake-upenableordisable(bitoption)PB0~PB7:wake-upenableordisable(bitoption)PC0~PC7:wake-upenableordisable(nibbleoption)Options10PD0~PD7:wake-upenableordisable(bitoption)11PE0~PE7:wake-upenableordisable(bitoption)12PF0~PF3:wake-upenableordisable(bitoption)13PA0~PA7:CMOSorNMOSoutputtype(bitoption)WatchdogOptions14WDT:enableordisable15CLRWDTinstructions:oneortwoinstructions16WDTClockSource:fSYS/4orWDToscillatorLVROptions17LVRfunction:enableordisableTBHPOptions18TBHPenableordisableRev.1.1059August5,2011

HT82A836RApplicationCircuits

Rev.1.1060August5,2011

HT82A836RInstructionSet

Introduction

Centraltothesuccessfuloperationofanymicrocontrollerisitsinstructionset,whichisasetofpro-graminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofpro-grammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes,theyhavebeensubdividedintoseveralfunc-tionalgroupings.InstructionTiming

Mostinstructionsareimplementedwithinoneinstruc-tioncycle.Theexceptionstothisarebranch,call,orta-blereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5msandbranchorcallinstructionswouldbeim-plementedwithin1ms.Althoughinstructionswhichre-quireonemorecycletoimplementaregenerallylimitedtotheJMP,CALL,RET,RETIandtablereadinstruc-tions,itisimportanttorealizethatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimple-ment.AsinstructionswhichchangethecontentsofthePCLwillimplyadirectjumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstruc-tionswouldbe²CLRPCL²or²MOVPCL,A².Forthecaseofskipinstructions,itmustbenotedthatifthere-sultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.MovingandTransferringData

Thetransferofdatawithinthemicrocontrollerprogramisoneofthemostfrequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimme-diatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromtheinputportsandtransferdatatotheoutputports.ArithmeticOperations

Theabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddand

subtractinstructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbetakentoen-surecorrecthandlingofcarryandborrowdatawhenre-sultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.LogicalandRotateOperations

ThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontrollerinstructionset.Aswiththecaseofmostinstructionsinvolvingdatamanipulation,datamustpassthroughtheAccumulatorwhichmayinvolveadditionalprogrammingsteps.Inalllogicaldataoperations,thezeroflagmaybesetiftheresultoftheoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonpro-gramrequirements.RotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregisterintotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

BranchesandControlTransfer

ProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasub-routineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall,theprogrammustreturntotheinstructionimmediatelywhenthesub-routinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmadere-gardingtheconditionofacertaindatamemoryorindi-vidualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithinthepro-gramperhapsdeterminedbytheconditionofcertainin-putswitchesorbytheconditionofinternaldatabits.

Rev.1.1061August5,2011

HT82A836RBitOperations

TheabilitytoprovidesinglebitoperationsonDataMem-oryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeatureisespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe²SET[m].i²or²CLR[m].i²instructionsrespectively.Thefea-tureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writepro-cessistakencareofautomaticallywhenthesebitoper-ationinstructionsareused.TableReadOperations

Datastorageisnormallyimplementedbyusingregis-ters.However,whenworkingwithlargeamountsoffixeddata,thevolumeinvolvedoftenmakesitinconve-nienttostorethefixeddataintheDataMemory.Toover-comethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstruc-tionsprovidesthemeansbywhichthisfixeddatacanbereferencedandretrievedfromtheProgramMemory.

OtherOperations

Inadditiontotheabovefunctionalinstructions,arangeofotherinstructionsalsoexistsuchasthe²HALT²in-structionforPower-downoperationsandinstructionstocontroltheoperationoftheWatchdogTimerforreliableprogramoperationsunderextremeelectricorelectro-magneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.InstructionSetSummary

Thefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbecon-sultedasabasicinstructionreferenceusingthefollow-inglistedconventions.Tableconventions:x:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbits

addr:Programmemoryaddress

MnemonicArithmeticADDA,[m]ADDMA,[m]ADDA,xADCA,[m]ADCMA,[m]SUBA,xSUBA,[m]SUBMA,[m]SBCA,[m]SBCMA,[m]DAA[m]ANDA,[m]ORA,[m]XORA,[m]ANDMA,[m]ORMA,[m]XORMA,[m]ANDA,xORA,xXORA,xCPL[m]CPLA[m]INCA[m]INC[m]DECA[m]DEC[m]DescriptionAddDataMemorytoACCAddACCtoDataMemoryAddimmediatedatatoACCAddDataMemorytoACCwithCarryAddACCtoDatamemorywithCarrySubtractimmediatedatafromtheACCSubtractDataMemoryfromACCSubtractDataMemoryfromACCwithresultinDataMemorySubtractDataMemoryfromACCwithCarrySubtractDataMemoryfromACCwithCarry,resultinDataMemoryDecimaladjustACCforAdditionwithresultinDataMemoryLogicalANDDataMemorytoACCLogicalORDataMemorytoACCLogicalXORDataMemorytoACCLogicalANDACCtoDataMemoryLogicalORACCtoDataMemoryLogicalXORACCtoDataMemoryLogicalANDimmediateDatatoACCLogicalORimmediateDatatoACCLogicalXORimmediateDatatoACCComplementDataMemoryComplementDataMemorywithresultinACCIncrementDataMemorywithresultinACCIncrementDataMemoryDecrementDataMemorywithresultinACCDecrementDataMemoryCycles11Note11Note111Note111Note1Note111FlagAffectedZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVZ,C,AC,OVCZZZZZZZZZZZZZZZLogicOperation1Note1Note1Note111Note111Increment&Decrement1Note11NoteRev.1.1062August5,2011

HT82A836RMnemonicRotateRRA[m]RR[m]RRCA[m]RRC[m]RLA[m]RL[m]RLCA[m]RLC[m]DataMoveMOVA,[m]MOV[m],AMOVA,xBitOperationCLR[m].iSET[m].iBranchJMPaddrSZ[m]SZA[m]SZ[m].iSNZ[m].iSIZ[m]SDZ[m]SIZA[m]SDZA[m]CALLaddrRETRETA,xRETITableReadTABRDC[m]TABRDL[m]MiscellaneousNOPCLR[m]SET[m]CLRWDTCLRWDT1CLRWDT2SWAP[m]SWAPA[m]HALTNote:

NooperationClearDataMemorySetDataMemoryClearWatchdogTimerPre-clearWatchdogTimerPre-clearWatchdogTimerSwapnibblesofDataMemorySwapnibblesofDataMemorywithresultinACCEnterpowerdownmode11Note1Note111Note111NoneNoneNoneTO,PDFTO,PDFTO,PDFNoneNoneTO,PDFReadtable(currentpage)toTBLHandDataMemoryReadtable(lastpage)toTBLHandDataMemory2Note2NoteNoneNoneJumpunconditionallySkipifDataMemoryiszeroSkipifDataMemoryiszerowithdatamovementtoACCSkipifbitiofDataMemoryiszeroSkipifbitiofDataMemoryisnotzeroSkipifincrementDataMemoryiszeroSkipifdecrementDataMemoryiszeroSkipifincrementDataMemoryiszerowithresultinACCSkipifdecrementDataMemoryiszerowithresultinACCSubroutinecallReturnfromsubroutineReturnfromsubroutineandloadimmediatedatatoACCReturnfrominterrupt11note1Note1Note1Note1Note1Note1Note2222NoteDescriptionRotateDataMemoryrightwithresultinACCRotateDataMemoryrightRotateDataMemoryrightthroughCarrywithresultinACCRotateDataMemoryrightthroughCarryRotateDataMemoryleftwithresultinACCRotateDataMemoryleftRotateDataMemoryleftthroughCarrywithresultinACCRotateDataMemoryleftthroughCarryMoveDataMemorytoACCMoveACCtoDataMemoryMoveimmediatedatatoACCClearbitofDataMemorySetbitofDataMemoryCycles1FlagAffectedNoneNoneCCNoneNoneCCNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone1111NoteNoteNoteNote1111Note111Note1Note21.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe²CLRWDT1²and²CLRWDT2²instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth²CLRWDT1²and²CLRWDT2²instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev.1.1063August5,2011

HT82A836RInstructionDefinition

ADCA,[m]DescriptionOperationAffectedflag(s)ADCMA,[m]DescriptionOperationAffectedflag(s)ADDA,[m]DescriptionOperationAffectedflag(s)ADDA,xDescriptionOperationAffectedflag(s)ADDMA,[m]DescriptionOperationAffectedflag(s)ANDA,[m]DescriptionOperationAffectedflag(s)ANDA,xDescriptionOperationAffectedflag(s)ANDMA,[m]DescriptionOperationAffectedflag(s)Rev.1.10

AddDataMemorytoACCwithCarry

ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]+COV,Z,AC,C

AddACCtoDataMemorywithCarry

ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]+COV,Z,AC,C

AddDataMemorytoACC

ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredintheAccumulator.ACC¬ACC+[m]OV,Z,AC,C

AddimmediatedatatoACC

ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded.TheresultisstoredintheAccumulator.ACC¬ACC+xOV,Z,AC,C

AddACCtoDataMemory

ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded.TheresultisstoredinthespecifiedDataMemory.[m]¬ACC+[m]OV,Z,AC,C

LogicalANDDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalANDop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²AND²[m]Z

LogicalANDimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalANDoperation.TheresultisstoredintheAccumulator.ACC¬ACC²AND²xZ

LogicalANDACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalANDop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²AND²[m]Z

August5,2011

HT82A836RCALLaddrDescription

Subroutinecall

Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthenin-crementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothestack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthisnewaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruc-tion.

Stack¬ProgramCounter+1ProgramCounter¬addrNone

ClearDataMemory

EachbitofthespecifiedDataMemoryisclearedto0.[m]¬00HNone

ClearbitofDataMemory

BitiofthespecifiedDataMemoryisclearedto0.[m].i¬0None

ClearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.WDTclearedTO¬0PDF¬0TO,PDF

Pre-clearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF

Pre-clearWatchdogTimer

TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunc-tionwithCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect.Re-petitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhavenoeffect.WDTclearedTO¬0PDF¬0TO,PDF

OperationAffectedflag(s)CLR[m]DescriptionOperationAffectedflag(s)CLR[m].iDescriptionOperationAffectedflag(s)CLRWDTDescriptionOperation

Affectedflag(s)CLRWDT1Description

Operation

Affectedflag(s)CLRWDT2Description

Operation

Affectedflag(s)

Rev.1.1065August5,2011

HT82A836RCPL[m]DescriptionOperationAffectedflag(s)CPLA[m]Description

ComplementDataMemory

EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.[m]¬[m]Z

ComplementDataMemorywithresultinACC

EachbitofthespecifiedDataMemoryislogicallycomplemented(1¢scomplement).Bitswhichpreviouslycontaineda1arechangedto0andviceversa.ThecomplementedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC¬[m]Z

Decimal-AdjustACCforadditionwithresultinDataMemory

ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)valuere-sultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibbleremainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadd-ing00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflagmaybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan100,itallowsmultipleprecisiondecimaladdition.[m]¬ACC+00Hor[m]¬ACC+06Hor[m]¬ACC+60Hor[m]¬ACC+66HC

DecrementDataMemory

DatainthespecifiedDataMemoryisdecrementedby1.[m]¬[m]-1Z

DecrementDataMemorywithresultinACC

DatainthespecifiedDataMemoryisdecrementedby1.TheresultisstoredintheAccu-mulator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]-1Z

Enterpowerdownmode

Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.ThecontentsoftheDataMemoryandregistersareretained.TheWDTandprescalerarecleared.ThepowerdownflagPDFissetandtheWDTtime-outflagTOiscleared.TO¬0PDF¬1TO,PDF

OperationAffectedflag(s)DAA[m]Description

Operation

Affectedflag(s)DEC[m]DescriptionOperationAffectedflag(s)DECA[m]DescriptionOperationAffectedflag(s)HALTDescription

OperationAffectedflag(s)

Rev.1.1066August5,2011

HT82A836RINC[m]DescriptionOperationAffectedflag(s)INCA[m]DescriptionOperationAffectedflag(s)JMPaddrDescription

IncrementDataMemory

DatainthespecifiedDataMemoryisincrementedby1.[m]¬[m]+1Z

IncrementDataMemorywithresultinACC

DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumu-lator.ThecontentsoftheDataMemoryremainunchanged.ACC¬[m]+1Z

Jumpunconditionally

ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Programexecutionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummyinstructionwhilethenewaddressisloaded,itisatwocycleinstruction.ProgramCounter¬addrNone

MoveDataMemorytoACC

ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.ACC¬[m]None

MoveimmediatedatatoACC

TheimmediatedataspecifiedisloadedintotheAccumulator.ACC¬xNone

MoveACCtoDataMemory

ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.[m]¬ACCNoneNooperation

Nooperationisperformed.Executioncontinueswiththenextinstruction.NooperationNone

LogicalORDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalORoper-ation.TheresultisstoredintheAccumulator.ACC¬ACC²OR²[m]Z

OperationAffectedflag(s)MOVA,[m]DescriptionOperationAffectedflag(s)MOVA,xDescriptionOperationAffectedflag(s)MOV[m],ADescriptionOperationAffectedflag(s)NOPDescriptionOperationAffectedflag(s)ORA,[m]DescriptionOperationAffectedflag(s)

Rev.1.1067August5,2011

HT82A836RORA,xDescriptionOperationAffectedflag(s)ORMA,[m]DescriptionOperationAffectedflag(s)RETDescriptionOperationAffectedflag(s)RETA,xDescriptionOperationAffectedflag(s)RETIDescription

LogicalORimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²OR²xZ

LogicalORACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalORoper-ation.TheresultisstoredintheDataMemory.[m]¬ACC²OR²[m]Z

Returnfromsubroutine

TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesatthere-storedaddress.

ProgramCounter¬StackNone

ReturnfromsubroutineandloadimmediatedatatoACC

TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecifiedimmediatedata.Programexecutioncontinuesattherestoredaddress.ProgramCounter¬StackACC¬xNone

Returnfrominterrupt

TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbyset-tingtheEMIbit.EMIisthemasterinterruptglobalenablebit.IfaninterruptwaspendingwhentheRETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbe-forereturningtothemainprogram.ProgramCounter¬StackEMI¬1None

RotateDataMemoryleft

ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.

[m].(i+1)¬[m].i;(i=0~6)[m].0¬[m].7None

RotateDataMemoryleftwithresultinACC

ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryre-mainunchanged.

ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬[m].7None

OperationAffectedflag(s)RL[m]DescriptionOperationAffectedflag(s)RLA[m]Description

OperationAffectedflag(s)

Rev.1.1068August5,2011

HT82A836RRLC[m]DescriptionOperation

RotateDataMemoryleftthroughCarry

ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.[m].(i+1)¬[m].i;(i=0~6)[m].0¬CC¬[m].7C

RotateDataMemoryleftthroughCarrywithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacestheCarrybitandtheoriginalcarryflagisrotatedintothebit0.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.(i+1)¬[m].i;(i=0~6)ACC.0¬CC¬[m].7C

RotateDataMemoryright

ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.

[m].i¬[m].(i+1);(i=0~6)[m].7¬[m].0None

RotateDataMemoryrightwithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0ro-tatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬[m].0None

RotateDataMemoryrightthroughCarry

ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.[m].i¬[m].(i+1);(i=0~6)[m].7¬CC¬[m].0C

RotateDataMemoryrightthroughCarrywithresultinACC

DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0re-placestheCarrybitandtheoriginalcarryflagisrotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremainunchanged.ACC.i¬[m].(i+1);(i=0~6)ACC.7¬CC¬[m].0C

Affectedflag(s)RLCA[m]Description

Operation

Affectedflag(s)RR[m]DescriptionOperationAffectedflag(s)RRA[m]Description

OperationAffectedflag(s)RRC[m]DescriptionOperation

Affectedflag(s)RRCA[m]Description

Operation

Affectedflag(s)

Rev.1.1069August5,2011

HT82A836RSBCA,[m]Description

SubtractDataMemoryfromACCwithCarry

ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]-COV,Z,AC,C

SubtractDataMemoryfromACCwithCarryandresultinDataMemory

ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagaresub-tractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthere-sultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]-COV,Z,AC,C

SkipifdecrementDataMemoryis0

ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]-1Skipif[m]=0None

SkipifdecrementDataMemoryiszerowithresultinACC

ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.ACC¬[m]-1SkipifACC=0None

SetDataMemory

EachbitofthespecifiedDataMemoryissetto1.[m]¬FFHNone

SetbitofDataMemory

BitiofthespecifiedDataMemoryissetto1.[m].i¬1None

OperationAffectedflag(s)SBCMA,[m]Description

OperationAffectedflag(s)SDZ[m]Description

OperationAffectedflag(s)SDZA[m]Description

OperationAffectedflag(s)SET[m]DescriptionOperationAffectedflag(s)SET[m].iDescriptionOperationAffectedflag(s)

Rev.1.1070August5,2011

HT82A836RSIZ[m]Description

SkipifincrementDataMemoryis0

ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.[m]¬[m]+1Skipif[m]=0None

SkipifincrementDataMemoryiszerowithresultinACC

ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,thefollowinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecifiedDataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummyin-structionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]+1SkipifACC=0None

SkipifbitiofDataMemoryisnot0

IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Skipif[m].i¹0None

SubtractDataMemoryfromACC

ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-[m]OV,Z,AC,C

SubtractDataMemoryfromACCwithresultinDataMemory

ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.TheresultisstoredintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.[m]¬ACC-[m]OV,Z,AC,C

SubtractimmediatedatafromACC

TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumu-lator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnega-tive,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.ACC¬ACC-xOV,Z,AC,C

OperationAffectedflag(s)SIZA[m]Description

OperationAffectedflag(s)SNZ[m].iDescription

OperationAffectedflag(s)SUBA,[m]Description

OperationAffectedflag(s)SUBMA,[m]Description

OperationAffectedflag(s)SUBA,xDescription

OperationAffectedflag(s)

Rev.1.1071August5,2011

HT82A836RSWAP[m]DescriptionOperationAffectedflag(s)SWAPA[m]DescriptionOperationAffectedflag(s)SZ[m]Description

SwapnibblesofDataMemory

Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.[m].3~[m].0«[m].7~[m].4None

SwapnibblesofDataMemorywithresultinACC

Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.TheresultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.ACC.3~ACC.0¬[m].7~[m].4ACC.7~ACC.4¬[m].3~[m].0None

SkipifDataMemoryis0

IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruc-tion.

Skipif[m]=0None

SkipifDataMemoryis0withdatamovementtoACC

ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero,thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruc-tionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.ACC¬[m]Skipif[m]=0None

SkipifbitiofDataMemoryis0

IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisre-quirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Skipif[m].i=0None

Readtable(currentpage)toTBLHandDataMemory

Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None

Readtable(lastpage)toTBLHandDataMemory

Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.[m]¬programcode(lowbyte)TBLH¬programcode(highbyte)None

OperationAffectedflag(s)SZA[m]Description

OperationAffectedflag(s)SZ[m].iDescription

OperationAffectedflag(s)TABRDC[m]DescriptionOperationAffectedflag(s)TABRDL[m]DescriptionOperationAffectedflag(s)

Rev.1.1072August5,2011

HT82A836RXORA,[m]DescriptionOperationAffectedflag(s)XORMA,[m]DescriptionOperationAffectedflag(s)XORA,xDescriptionOperationAffectedflag(s)

LogicalXORDataMemorytoACC

DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXORop-eration.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²[m]Z

LogicalXORACCtoDataMemory

DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXORop-eration.TheresultisstoredintheDataMemory.[m]¬ACC²XOR²[m]Z

LogicalXORimmediatedatatoACC

DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXORoperation.TheresultisstoredintheAccumulator.ACC¬ACC²XOR²xZ

Rev.1.1073August5,2011

HT82A836RPackageInformation

Notethatthepackageinformationprovidedhereisforconsultationpurposesonly.Asthisinformationmaybeupdatedatregu-larintervalsusersareremindedtoconsulttheHoltekwebsite(http://www.holtek.com.tw/english/literature/package.pdf)forthelatestversionofthepackageinformation.

80-pinLQFP(10mm´10mm)OutlineDimensions

SymbolABCDEFGHIJKaSymbolABCDEFGHIJKaRev.1.10

DimensionsininchMin.0.4690.3900.4690.390¾¾0.053¾¾0.0180.0040°Nom.¾¾¾¾0.0160.006¾¾0.004¾¾¾DimensionsinmmMin.11.909.9011.909.90¾¾1.35¾¾0.450.100°74

Nom.¾¾¾¾0.400.16¾¾0.10¾¾¾Max.12.1010.1012.1010.10¾¾1.451.60¾0.750.207°August5,2011Max.0.4760.3980.4760.398¾¾0.0570.063¾0.0300.0087°HT82A836RHoltekSemiconductorInc.(Headquarters)

No.3,CreationRd.II,SciencePark,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-11http://www.holtek.com.tw

HoltekSemiconductorInc.(TaipeiSalesOffice)

4F-2,No.3-2,YuanQuSt.,NankangSoftwarePark,Taipei115,TaiwanTel:886-2-2655-7070Fax:886-2-2655-7373

Fax:886-2-2655-7383(Internationalsaleshotline)

HoltekSemiconductor(China)Inc.(DongguanSalesOffice)

BuildingNo.10,XinzhuCourt,(No.1Headquarters),4CuizhuRoad,SongshanLake,Dongguan,China523808Tel:86-769-2626-1300Fax:86-769-2626-1311

HoltekSemiconductor(USA),Inc.(NorthAmericaSalesOffice)46729FremontBlvd.,Fremont,CA94538,USATel:1-510-252-9880Fax:1-510-252-9885http://www.holtek.com

CopyrightÓ2006byHOLTEKSEMICONDUCTORINC.

TheinformationappearinginthisDataSheetisbelievedtobeaccurateatthetimeofpublication.However,Holtekas-sumesnoresponsibilityarisingfromtheuseofthespecificationsdescribed.TheapplicationsmentionedhereinareusedsolelyforthepurposeofillustrationandHoltekmakesnowarrantyorrepresentationthatsuchapplicationswillbesuitablewithoutfurthermodification,norrecommendstheuseofitsproductsforapplicationthatmaypresentarisktohumanlifeduetomalfunctionorotherwise.Holtek¢sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystems.Holtekreservestherighttoalteritsproductswithoutpriornotification.Forthemostup-to-dateinformation,pleasevisitourwebsiteathttp://www.holtek.com.tw.

Rev.1.1075August5,2011