RTL8212

RTL8212-GRRTL8212N-GR

RTL8211N-GR

INTEGRATED 10/100/1000 SINGLE/DUAL GIGABIT ETHERNET TRANSCEIVER

DATASHEET

Rev. 1.2

15 November 2005 Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw

RTL8212/RTL8212N/RTL8211N Datasheet COPYRIGHT

©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek RTL8212/RTL8212N/RTL8211N Integrated Circuits.

Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY

Revision Release Date Summary 1.0 2005/08/10 First release. 1.1 2005/09/09 1. Add RTL8211N-GR single PHYceiver.

2. Correct typo for page 20 P0RXDV description.

1.2 2005/11/15 1. Update datasheet and product name to RTL8212, RTL8212N and

RTL8211N.

2. Remove RSGMII interface from RTL8212 (QFP-128).

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver ii Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet Table of Contents

1. 2. 3. 4. 5. 6.

General Description....................................................................................................9 Features......................................................................................................................10 System Applications..................................................................................................10 System Application Diagrams..................................................................................11 Block Diagram...........................................................................................................13 Pin Assignments.........................................................................................................14

6.1. RTL8212 EDHS QFP-128 PACKAGE.............................................................................................14 6.2. PACKAGE IDENTIFICATION (RTL8212 EDHS QFP-128)...............................................................14 6.3. RTL8212N QFN-76 PACKAGE......................................................................................................15 6.4. PACKAGE IDENTIFICATION (RTL8212N QFN-76).........................................................................15 6.5. RTL8211N QFN-76 PACKAGE......................................................................................................16 6.6. PACKAGE IDENTIFICATION (RTL8211N QFN-76).........................................................................16

7. Pin Descriptions.........................................................................................................17

7.1. MEDIA DEPENDENT INTERFACE PINS.............................................................................................17 7.2. GMII/MII TRANSMIT INTERFACE PINS..........................................................................................18 7.3. GMII/MII RECEIVE INTERFACE PINS.............................................................................................19 7.4. RGMII TRANSMIT INTERFACE PINS...............................................................................................20 7.5. RGMII RECEIVE INTERFACE PINS..................................................................................................21 7.6. RSGMII INTERFACE PINS..............................................................................................................21 7.7. SERIAL MANAGEMENT INTERFACE PINS........................................................................................22 7.8. SERIAL LED INTERFACE PINS........................................................................................................22 7.9. SYSTEM CLOCK INTERFACE PINS...................................................................................................23 7.10. CONFIGURATION AND CONTROL PINS............................................................................................24 7.11. MISCELLANEOUS PINS....................................................................................................................25 7.12. POWER AND GROUND PINS.............................................................................................................26

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver iii Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.

Functional Description..............................................................................................27

8.1. MDI INTERFACE.............................................................................................................................27 8.1.1. Crossover Detection and Auto Correction............................................................................................................27 8.1.2. Polarity Correction...............................................................................................................................................28 8.1.3. MAC Interface......................................................................................................................................................29 8.2. GIGABIT MEDIA INDEPENDENT INTERFACE (GMII/MII)................................................................30 8.2.1. Reduced GMII (RGMII).......................................................................................................................................32 8.2.2. 10/100 Functionality............................................................................................................................................33 8.2.3. TX_CTL and RX_CTL Coding..............................................................................................................................34 8.2.4. In-Band Status......................................................................................................................................................36 8.2.5. Four RGMII Modes..............................................................................................................................................36 8.3. REDUCED SERIAL GMII (RSGMII)................................................................................................37 8.3.1. RSGMII Data Transfer.........................................................................................................................................39 8.4. MDC/MDIO MANAGEMENT INTERFACE.......................................................................................40 8.4.1. Preamble Suppression..........................................................................................................................................41 8.5. HARDWARE CONFIGURATION INTERFACE......................................................................................42 8.6. LED CONFIGURATION....................................................................................................................43 8.6.1. LED System Application Examples......................................................................................................................43 8.6.2. Serial Stream Order..............................................................................................................................................44 8.7. SYSTEM CLOCK INTERFACE...........................................................................................................44 8.8. REGISTER DESCRIPTIONS................................................................................................................45 8.8.1. Register Symbols..................................................................................................................................................45 8.8.2. MII Specification Defined Registers.....................................................................................................................45 8.8.3. Register0: Control................................................................................................................................................46 8.8.4. Register1: Status...................................................................................................................................................47 8.8.5. Register2: PHY Identifier 1 Register....................................................................................................................48

8.8.6. 8.8.7. 8.8.8. 8.8.9. 8.8.11.

Register3: PHY Identifier 2 Register....................................................................................................................48 Register4: Auto-Negotiation Advertisement.........................................................................................................49 Register5: Auto-Negotiation Link Partner Ability................................................................................................50 Register6: Auto-Negotiation Expansion...............................................................................................................51 Register8: Auto-Negotiation Link Partner Next Page Register............................................................................52

8.8.10. Register7: Auto-Negotiation Page Transmit Register..........................................................................................51 8.8.12. Register9: 1000Base-T Control Register..............................................................................................................52 8.8.13. Register10: 1000Base-T Status Register..............................................................................................................53 8.8.14. Register15: Extended Status.................................................................................................................................53

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver

iv Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 9.

Characteristics...........................................................................................................54

9.1. ABSOLUTE MAXIMUM RATINGS.....................................................................................................54 9.2. OPERATING RANGE........................................................................................................................54 9.3. DC CHARACTERISTICS...................................................................................................................55 9.4. AC CHARACTERISTICS...................................................................................................................57

10. Design and Layout Guide.........................................................................................59

10.1. GENERAL GUIDELINES...................................................................................................................59 10.2. MII/GMII/RGMII SIGNAL LAYOUT GUIDELINES..........................................................................59 10.3. RSGMII SIGNAL LAYOUT GUIDELINES..........................................................................................60 10.4. ETHERNET MDI DIFFERENTIAL SIGNAL LAYOUT GUIDELINES......................................................60 10.5. CLOCK CIRCUIT..............................................................................................................................60 10.6. POWER PLANES..............................................................................................................................60 10.7. GROUND PLANE.............................................................................................................................61 10.8. TRANSFORMER OPTIONS................................................................................................................61

11. Mechanical Dimensions............................................................................................62

11.1. EDHS-QFP-128 DIMENSIONS (RTL8212).....................................................................................62 11.2. NOTES FOR EDHS-QFP-128 DIMENSIONS (RTL8212)..................................................................63 11.3. QFN-76 DIMENSIONS (RTL8211N & RTL8212N)........................................................................ 11.4. NOTES FOR QFN-76 DIMENSIONS (RTL8211N & RTL8212N).....................................................65

12. Ordering Information...............................................................................................66

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver v Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet List of Tables

Table 1. Pin Type Abbreviations.............................................................................................................17 Table 2. Media Dependent Interface Pins...............................................................................................17 Table 3. GMII/MII Transmit Interface Pins............................................................................................18 Table 4. GMII/MII Receive Interface Pins.............................................................................................19 Table 5. RGMII Transmit Interface Pins................................................................................................20 Table 6. RGMII Receive Interface Pins..................................................................................................21 Table 7. RSGMII Interface Pins.............................................................................................................21 Table 8. Serial Management Interface Pins............................................................................................22 Table 9. Serial LED Interface Pins.........................................................................................................22 Table 10. System Clock Interface Pins.....................................................................................................23 Table 11. Configuration and Control Pins................................................................................................24 Table 12. Miscellaneous Pins....................................................................................................................25 Table 13. Power and Ground Pins............................................................................................................26 Table 14. Mapping of Twisted-Pair Outputs to RJ-45 Connectors...........................................................27 Table 15. Media Dependent Interface Pin Mapping.................................................................................27 Table 16. Data Rates Supported Through Each Interface.........................................................................29 Table 17. MAC Interface Modes of Operation.........................................................................................29 Table 18. Gigabit Media Independent Interface.......................................................................................30 Table 19. MAC Interface Modes of Operation.........................................................................................32 Table 20. TX_ER and TX_EN Encoding.................................................................................................34 Table 21. RX_ER and RX_DV Encoding................................................................................................35 Table 22. RGMII Timing Modes..............................................................................................................36 Table 23. Configuration Pin Definitions...................................................................................................42 Table 24. LED Mode................................................................................................................................43 Table 25. LED Status................................................................................................................................43 Table 26. Serial Stream Order (Mode 0)...................................................................................................44 Table 27. Serial Stream Order (Mode 1)...................................................................................................44 Table 28. MII Specification Defined Registers........................................................................................45 Table 29. Register0: Control.....................................................................................................................46 Table 30. Register1: Status.......................................................................................................................47 Table 31. Register2: PHY Identifier 1 Register........................................................................................48 Table 32. Register3: PHY Identifier 2 Register........................................................................................48 Table 33. Register4: Auto-Negotiation Advertisement.............................................................................49

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver

vi Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet Table 34. Register5: Auto-Negotiation Link Partner Ability....................................................................50 Table 35. Register6: Auto-Negotiation Expansion...................................................................................51 Table 36. Register7: Auto-Negotiation Page Transmit Register...............................................................51 Table 37. Register8: Auto-Negotiation Link Partner Next Page Register................................................52 Table 38. Register9: 1000Base-T Control Register..................................................................................52 Table 39. Register10: 1000Base-T Status Register...................................................................................53 Table 40. Register15: Extended Status.....................................................................................................53 Table 41. Absolute Maximum Ratings.....................................................................................................54 Table 42. Operating Range.......................................................................................................................54 Table 43. DC Characteristics....................................................................................................................55 Table 44. Digital Timing Characteristics..................................................................................................58 Table 45. Ordering Information................................................................................................................66

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver vii Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet List of Figures

Figure 1. RTL8212N with 8-Port Gigabit MAC (RTL8369).................................................................11 Figure 2. RTL8212 with 24+2G MAC (RTL8326)................................................................................12 Figure 3. Block Diagram........................................................................................................................13 Figure 4. Pin Assignments (RTL8212 EDHS QFP-128)........................................................................14 Figure 5. Pin Assignments (RTL8212N QFN-76)..................................................................................15 Figure 6. Pin Assignments (RTL8211N QFN-76)..................................................................................16 Figure 7. Conceptual Example of Polarity Correction...........................................................................28 Figure 8. GMII Signal Diagram..............................................................................................................30 Figure 9. MII Signal Diagram................................................................................................................31 Figure 10. RGMII Signal Diagram...........................................................................................................33 Figure 11. RGMII Data Transmission......................................................................................................34 Figure 12. RGMII Data Reception Without Error....................................................................................35 Figure 13. RGMII Data Reception With Error.........................................................................................35 Figure 14. RSGMII Interconnection Diagram..........................................................................................37 Figure 15. Realtek 8G Switch Application with RSGMII........................................................................38 Figure 16. RSGMII Functional Block Diagram at Ethernet PHY Side....................................................39 Figure 17. RSGMII Functional Block Diagram at Ethernet MAC Side...................................................40 Figure 18. MDIO Read Frame Format.....................................................................................................41 Figure 19. MDIO Write Frame Format.....................................................................................................41 Figure 20. Clock Generated from MAC (RSGMII Mode).......................................................................44 Figure 21. MII Interface Reception Data Timing.....................................................................................57 Figure 22. MII Interface Transmission Data Timing................................................................................57

Integrated 10/100/1000 Single/ Dual Gigabit Ethernet Transceiver viii Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 1. General Description

The RTL8212/RTL8212N/8211N integrate dual/single independent Gigabit Ethernet transceivers into a single IC and performs all the physical layer (PHY) functions for 10Base-T, 100Base-TX, and 1000Base-T Ethernet on category 3 (10Base-T) or category 5 UTP cable (except 1000Base-T half duplex operation).

The device includes the PCS, PMA, and PMD sub-layers. They perform encoding/decoding, clock/data recovery, digital adaptive equalization, echo cancellers, cross-talk elimination, line driver, as well as all other required support circuit functions. The device also integrates an internal hybrid that allows the use of inexpensive 1:1 transformer modules.

Each of the two independent transceivers features an industrial standard GMII, MII, and RGMII (Reduced Gigabit Media Independent Interface). To further reduce PCB trace complexity, the RTL8211N/8212N also provides an innovative 2.5Gbps serial interface – the Reduced Serial Gigabit Media Independent Interface (RSGMII). Both dual transceivers can simultaneously communicate with the MAC through the same RSGMII interface.

The RTL8212/RTL8212N/8211N adopts mixed mode 0.13µm CMOS technology and analog line driver architecture that offers lower power consumption than DAC architecture.

Two package types are available; a thermally-enhanced 128-pin EDHS-QFP (Exposed Drop-in Heat Sink QFP) package, and a QFN (Quad Flat No-Lead) 76-pin package.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 9 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 2. Features

󰂄 Single/Dual integrated 10/100/1000Base-T Gigabit Ethernet transceiver 󰂄 Supports full duplex at 10/100/1000Mbps, and half duplex at 10/100Mbps

󰂄 Supports 2.5V I/O (3.3V input tolerance) GMII and RGMII interfaces in 10/100/1000

mode for RTL8212 (QFP-128 Package)

󰂄 Supports RSGMII (2.5Gbps serial high speed interface) in 10/100/1000 mode for

RTL8212N and RTL8211N (QFN-76 Package) 󰂄 Crossover detection and auto correction at all 3 speeds

󰂄 Automatic detection and correction of wiring pair swaps, pair skew, and pair polarity 󰂄 Supports serial LED mode

󰂄 Line driver architecture with low power dissipation PAVE= 0.78W/port

󰂄 3.3V, 1.8V, and 1.2V power supply (2.5V is generated by internal linear regulator for

Digital I/O pads) 󰂄 Packages:

󰂋 󰂋

EDHS QFP-128, 14x20mm, 0.5mm lead pitch package QFN-76, 9x9mm, 0.4mm pitch package

󰂄 0.13µm CMOS process

3. System Applications

󰂄 High-density Gigabit Ethernet switches and routers

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

10 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 4. System Application Diagrams

RTL8369 8-Port Ethernet MACMAC Interface:RSGMIIRTL8212NDual-PHY(10/100/1000)RTL8212NDual-PHY(10/100/1000)RTL8212NDual-PHY(10/100/1000)RTL8212NDual-PHY(10/100/1000)MagneticsRJ-45RJ-45RJ-45RJ-45

RJ-45RJ-45RJ-45RJ-45Figure 1. RTL8212N with 8-Port Gigabit MAC (RTL8369)

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 11 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet RTL8326 24+2G Ethernet MACMAC Interface:GMII/MII -RGMIIRTL8212Dual-PHY(10/100/1000)RTL8208Octa-PHY(10/100)RTL8208Octa-PHY(10/100)RTL8208Octa-PHY(10/100)MagneticsRJ-45RJ-45RJ-45 * 8RJ-45 * 8RJ-45 * 8

Figure 2. RTL8212 with 24+2G MAC (RTL8326)

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 12 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 5. Block Diagram

Equalizer&Echo,NEXT,FEXT,CancellersAGC,TimingRecovery,WanderCancellerPnTXD[7..0]

PnGTXCPnTXENPnTXCPnCOLPnCRSPnRXD[7..0]

PnRXCPnRXDVPnRXER

GMIIorRGMIIorRSGMII1000Base-Tx4DPAM5EnDec,Scrambler,Viterbi,& DFEA/DHybridPAIR A

PulseShaperD/AFilterLine-DriverTwisted-PairinterfacePAIR B

PAIR C

100Base-Tx4B/5BEnDecScrambler/DescramblerSTXPSTXNSRXPSRXNSDS_REF

FilterPAIR D

10Base-TManchesterEnDecMDI (Analog Front End)PORT 0PORT 1XTAL1XTAL2

CLK25M-INCLK25M-OUTLEDCKLEDDA

Auto NegotiationMDCMDIO

PHYADD[4..1]MODE[2..0]INTF_SEL[2..0]

RESETB

PLLSerial-LEDSerialManagement & ModeSelect LogicMII RegisterBiasingMDI_REF

Figure 3. Block Diagram

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 13 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 6. Pin Assignments

6.1. RTL8212 EDHS QFP-128 Package P0RXD1P0RXD2/PHYADR[1]VSS12VDD12P0RXD3/PHYADR[2]P0RXD4/PHYADR[3]P0RXD5/PHYADR[4]VSS12P0RXD6/INTF_SEL[0]P0RXD7/INTF_SEL[1]VDD12P1TXD7VDDIOSVDD12NCNCAVSSCLKINAVSSNCNCSVDD18P1TXD6P1TXD5P1TXD4VSS12P1TXD3P1TXD2VDD12P1TXD1P1TXD0VDDIOP1TXENP1GTXCP1TXCVSS12VDD12P1CRS/P1MODE[0]VDDIOVSSIOVDD12

DIS_AUTOXOVER/ P0RXD0

P0MODE[3]/ P0RXDV

VSS12P0RXC

P0MODE[2]/ P0RXER

VDD12VSS12RVDD33

P0MODE[1]/ P0COLP0MODE[0]/ P0CRS

P0TXCP0GTXCP0TXENVDDIOP0TXD0P0TXD1P0TXD2P0TXD3P0TXD4P0TXD5P0TXD6P0TXD7MDIO

103104105106107108109110111112113114115116117118119120121122123124125126127128102101100999796959493929190888786858483828180797877767574737271706968676665636261605958575655545352515049484745444342414039RTL8212LLLLLLL TXXXVP1COL /P1MODE[1]P1RXER /P1MODE[2]P1RXCVSS12

P1RXDV /P1MODE[3]P1RXD0VDD12VDDIOP1RXD1

P1RXD2 /RXDLYP1RXD3 /TXDLYVSS12

P1RXD4/LEDMODEP1RXD5VDD12P1RXD6P1RXD7VSSIORVDD33RESETBVDDIOAVSSXTAL1XTAL2AVDD12AVDD33

MDCLEDCKLEDDAAVDD33ATESTAVDD18P0MDIAPP0MDIANAVSSP0MDIBPP0MDIBNAVDD18P0MDICPP0MDICNAVSSP0MDIDPP0MDIDNAVDD18AVDD33P1MDIAPP1MDIANAVSSP1MDIBPP1MDIBNAVDD18P1MDICPP1MDICNAVSSP1MDIDPP1MDIDNAVDD18AVDD33AVDDPLLAVSSPLLMDI_REFAVSSRTT1RTT212345671011121314151617181920212223242526272829303132333435363738

Figure 4. Pin Assignments (RTL8212 EDHS QFP-128)

6.2. Package Identification (RTL8212 EDHS QFP-128) Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 4.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

14 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 6.3. RTL8212N QFN-76 Package VDD12PHYADR[2]PHYADR[3]PHYADR[4]VDD12VDDIOSVDD12STXNSTXPSVSS12CLKINSVSS18SRXNSRXPSVDD18VDD12VDDIONCVDD12575655545352515049484745444342414039P0MDIAPP0MDIANP0MDIBPP0MDIBNAVDD18P0MDICPP0MDICNP0MDIDPP0MDIDNAVDD18P1MDIAPP1MDIANP1MDIBPP1MDIBNAVDD18P1MDICPP1MDICNP1MDIDPP1MDIDN123456710111213141516171819PHYADR[1]

NCVDDIOVDD12

DIS_AUTOXOVER

P0MODE[3]P0MODE[2]

VDD12RVDD33P0MODE[1]P0MODE[0]

VDDIOMDIOMDCLEDCKLEDDAAVDD33AVDD18

NC

585960616263656667686970717273747576RTL8212NLLLLLLL TXXXV38373635343332313029282726252423222120P1MODE[0]P1MODE[1]P1MODE[2]P1MODE[3]VDD12VDDIONCVDD12RVDD33RESETBVDDIOAVDD12AVDD33RTT2RTT1MDIREFAVDDPLLAVDD33AVDD18

Figure 5. Pin Assignments (RTL8212N QFN-76)

6.4. Package Identification (RTL8212N QFN-76) Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 5.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

15 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 6.5. RTL8211N QFN-76 Package

Figure 6. Pin Assignments (RTL8211N QFN-76)

6.6. Package Identification (RTL8211N QFN-76) Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 6.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 16 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7. Pin Descriptions

Table 1. Pin Type Abbreviations Pin Type Definition I Input O Output I/O Bi-directional B Bias PU Internal pull-up PD Internal pull-down PWR Power GND Ground Note: The RTL8212/RTL8212N/RTL8211N is a dual-port/single Gigabit Ethernet transceiver. Each port, defined as Port0 and Port1 (Port 0 for RTL8211N), is independent of the other, and is identical in performance and functionality. In this document, these pins for each port are specified by the port number, pin name, and signal number, respectively.

For example, GMII transmit data pin 7 for port0 is shown as: P0TXD7

7.1. Media Dependent Interface Pins Table 2. Media Dependent Interface Pins

QFN76 Pin# 1, 2 3, 4 6, 7 8, 9 11, 12 13, 14 16, 17 18, 19

QFP128 Pin# 7, 8 10, 11 13, 14 16, 17 20, 21 23, 24 26, 27 29, 30

Pin Name P0MDIAP/N P0MDIBP/N P0MDICP/N P0MDIDP/N P1MDIAP/N P1MDIBP/N P1MDICP/N P1MDIDP/N

Type I/O

Description

Media Dependent Interface A~D. For 1000Base-T operation, differential data from the media is transmitted and received on all four pairs. For 100Base-Tx and 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs MDIAP/N and MDIBP/N.

Each of the differential pairs has an internal 100ohm termination resister.

Pins 11, 12, 13, 14, 16, 17, 18, and 19 of the QFN-76 package are N.C pins for the RTL8211N-GR.

TheRTL8211N-GR is available in a QFN-76 package only.

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RTL8212/RTL8212N/RTL8211N Datasheet 7.2. GMII/MII Transmit Interface Pins Table 3. GMII/MII Transmit Interface Pins

QFN76 QFP128 Pin Name Pin# Pin#

117 P0GTXC

69 P1GTXC 116 P0TXC 68 P1TXC

Type I O

Description

GMII Transmit Clock. 125MHz input clock. All transmit inputs must be synchronized to this clock during 1000Base-T

operation. This clock can be stopped in 10/100Base-T modes, and also during Auto-Negotiation.

MII Transmit Clock. All transmit inputs must be synchronized to this clock during 10/100 operation. It provides a 25MHz clock reference in 100Base-TX mode, and 2.5MHz clock reference in 10Base-T.

The 25MHz clock is the default rate.

GMII/MII Transmit Enable. The synchronous input indicates that valid data is being driven on the TXD bus. As the RTL8212 does not support 1000Base-T half-duplex mode, the

carrier-extension symbol is not transmitted onto the cable.

TXEN is synchronous to GTXC in 1000Base-T mode and synchronous to TXC in 10/100Base-TX mode.

GMII/MII Transmit Data Bus. The width of this synchronous input bus varies with the speed mode: 1000: TXD[7:0] are used.

10/100: TXD[3:0] are used; TXD[7:4] are ignored.

TXD[7:0] is synchronous to GTXC in 1000Base-T mode and synchronous to TXC in 10/100Base-TX mode.

118 P0TXEN

70 P1TXEN

I

127 126 125 124 123 122 121 120 91 80 79 78 76 75 73 72 P0TXD7 P0TXD6 P0TXD5 P0TXD4 P0TXD3 P0TXD2 P0TXD1 P0TXD0 P1TXD7 P1TXD6 P1TXD5 P1TXD4 P1TXD3 P1TXD2 P1TXD1 P1TXD0

IPD

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RTL8212/RTL8212N/RTL8211N Datasheet 7.3. GMII/MII Receive Interface Pins Table 4. GMII/MII Receive Interface Pins

QFN76 QFP128 Pin Name Pin# Pin#

109 P0RXC

62 P1RXC

Type OPD

Description

GMII/MII Receive Clock. The GMII/MII Receive output clock is used to synchronize received signals. Its frequency depends upon the link speed: 1000: 125MHz 100: 25MHz 10: 2.5MHz

GMII/MII Receive Data valid. This synchronous output is asserted when valid data is driven on RXD.

RXDV is synchronous to RXC.

GMII/MII Carrier Sense. This asynchronous output is asserted when a non-idle condition is detected at the twisted-pair interface, and de-asserted when idle or a valid end of stream delimiter is detected. In 10/100Base-T half duplex, CRS is also asserted during transmission.

CRS is asynchronous to TXC and RXC.

GMII/MII Collision. This asynchronous output is asserted when a collision is detected in half-duplex modes. In full duplex mode, this out is forced low.

COL is asynchronous to TXC, and RXC.

GMII/MII Receive Error. When RXER and RXDV are both asserted, the symbol indicates an error symbol is detected on the cable. Since RTL8212 don’t support 1000Base-T half-duplex mode, carrier-extension receive symbol (RXER is asserted with RXDV deasserted) is not valid.

RXDV is synchronous to RXC.

107 P0RXDV

60 P1RXDV

OPD

115 P0CRS 65 P1CRS

OPD

114 P0COL P1COL

OPD

110 P0RXER 63 P1RXER

OPD

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RTL8212/RTL8212N/RTL8211N Datasheet QFN76 QFP128 Pin Name Pin# Pin#

P0RXD7 93 P0RXD6 94

P0RXD5 96

P0RXD4 97

P0RXD3 98

P0RXD2 101

P0RXD1 102

P0RXD0 106

P1RXD7 48

P1RXD6 49

P1RXD5 51

P1RXD4 52

P1RXD3 54

P1RXD2 55

P1RXD1 56

P1RXD0 59

Type OPD

Description

GMII/MII Receive Data Bus. The width of this synchronous

output bus varies with the speed mode: 1000: RXD[7:0] are used.

10/100: RXD[3:0] are used; RXD[7:4] are ignored.

RXD[7:0] is synchronous to RXC.

7.4. RGMII Transmit Interface Pins Table 5. RGMII Transmit Interface Pins

QFN76 QFP128 Pin Name Pin# Pin#

117 P0GTXC

69 P1GTXC

Type I

Description

RGMII Transmit Clock. All transmit inputs must be

synchronized to this clock. Its frequency, with +/- 50ppm tolerance, depends upon the link speed: 1000: 125MHz 100: 25MHz 10: 2.5MHz

RGMII Transmit Data Bus. In RGMII 1000Base-T mode,

TXD[3..0] runs at a double data rate with bits[3..0] presented on the rising edge of the GTXC, and bits[7..4] presented on the falling edge of the GTXC. TXD[7..4] are ignored in this mode.

In RGMII 10/100Base-T modes, the transmitted data nibble is presented on TXD[3..0] on the rising edge of GTXC and duplicated on the falling edge of GTXC.

RGMII Transmit Control. In RGMII mode, TXEN is used as TXCTL. TXEN is presented on the rising edge of GTXC.

A logical derivative of TXEN and TXER is presented on the falling edge of GTXC.

123 P0TXD3

122 P0TXD2 121 P0TXD1 120 P0TXD0 76 P1TXD3 75 P1TXD2 73 P1TXD1 72 P1TXD0

118 P0TXEN/

P0TXCTL 70 P1TXEN/

P1TXCTL

IPD

IPD

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 20 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.5. RGMII Receive Interface Pins Table 6. RGMII Receive Interface Pins

QFN76 QFP128 Pin Name Pin# Pin#

109 P0RXC

62 P1RXC

Type O

Description

RGMII Receive Clock. All RGMII receive outputs must be synchronized to this clock. Its frequency, with +/- 50ppm tolerance, depends upon the link speed: 1000: 125MHz 100: 25MHz 10: 2.5MHz

RGMII Receive Data Bus. In RGMII 1000Base-T mode,

RXD[3..0] runs at a double data rate with bits[3..0] presented on the rising edge of the RXC and bits[7..4] presented on the falling edge of the RXC. RXD[7..4] are ignored in this mode.

In RGMII 10/100Base_T modes, the received data nibble is presented on RXD[3..0] on the rising edge of RXC and duplicated on the falling edge of RXC.

RGMII Receive Control. In RGMII mode, RXDV is used as RXCTL. RXDV is presented on the rising edge of RXC.

A logical derivative of RXDV and RXER is presented on the falling edge of RXC.

P0RXD3 98 P0RXD2 101

P0RXD1 102

P0RXD0 106

P1RXD3 54

P1RXD2 55

P1RXD1 56

P1RXD0 59

107 P0RXCTL/

P0RXDV 60 P1RXCTL/

P1RXDV

OPD

OPD

7.6. RSGMII Interface Pins Table 7. RSGMII Interface Pins

QFN76

Pin# 44 45 49 50

QFP128 Pin Name Type Pin#

N/A SRXP O

SRXN

N/A STXP I

STXN

Description

RSGMII Receive Pair. 2.5GHz differential serial output.

The differential pair has an internal 100ohm termination resister.RSGMII Transmit Pair. 2.5GHz differential serial input.

The differential pair has an internal 100ohm termination resister.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 21 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.7. Serial Management Interface Pins Table 8. Serial Management Interface Pins

QFN76 QFP128 Pin Name Type Description Pin# Pin#

71 1 MDC I Management Data Clock. The clock reference for the serial

management interface.

70 128 MDIO I/OPU Management Data Input/Output. MDIO transfer management

data; in and out of the device synchronous to the rising edge of MDC.

OPD PHY Address Select. These pins are the four uppermost bits of 54 96 PHYADR[4]/

the 5-bit IEEE-specified PHY address. The states of these four P0RXD5

pins are latched during power-up or reset. 55 97 PHYADR[3]/

P0RXD4

The lowest bit of the 5-bit PHY address is hard-wired to each of 56 98 PHYADR[2]/

the dual ports within the device. ‘0’ represents Port0, and ‘1’

P0RXD3

represents Port1.

58 101 PHYADR[1]/

P0RXD2

7.8. Serial LED Interface Pins Table 9. Serial LED Interface Pins

QFN76 QFP128 Pin Name Type Description Pin# Pin#

72 2 LEDCK O Serial LED Clock. Reference output clock for serial LED

interface.

The 12.5MHz clock outputs periodically. Data is latched on the rising edge of LEDCK.

73 3 LEDDA O Serial LED Data Output. Serial bit stream of link status

information.

32 52 LEDMODE/ OPD Serial LED Mode Select. These pins are used to configure LED

operation mode. The state of this pin is latched during power-up P1RXD4

or reset. There are two LED display modes: 0: Mode 0 1: Mode 1

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 22 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.9. System Clock Interface Pins Table 10. System Clock Interface Pins

QFN76 QFP128 Pin Name Type Description Pin# Pin#

42 XTAL1 I PHY Reference Clock Input. 25MHz +/- 50ppm tolerance crystal

reference or oscillator input. When using a crystal, connect a loading capacitor from each pad to ground.

When CLKIN is used this pin is not valid and should be pulled-low.

The maximum XTAL1 input voltage is 1.8 V.

41 XTAL2 O PHY Reference Clock Output. 25MHz +/- 50ppm tolerance crystal

reference or oscillator output.

When CLKIN is used this pin is not valid and should be floating.

47 CLKIN I 25MHz Clock Input. 25MHz +/- 50ppm tolerance clock input.

When RSGMII is used this pin is able to accept a 25MHz clock signal generated from the MAC device (RTL8212N/RTL8211N only).

The maximum CLKIN input voltage is 1.8V.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 23 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.10. Configuration and Control Pins Table 11. Configuration and Control Pins

QFN76 QFP128 Pin Name

Pin# Pin#

93 INTF_SEL[1]/

P0RXD7 94 INTF_SEL[0]/

P0RXD6

Type Description OPD

MAC Interface mode select. INTF_SEL[1:0] determines the MAC interface configuration for both port0 and port1: 00: RSGMII (default mode) 01: GMII 10: RGMII 11: Reserved

P0MODE[3]/ OPD Auto-Negotiation Configuration. PxMODE[3:0] presets each port’s 107 63

advertise link ability (speed, duplex, and master/slave). The states of P0RXDV

this pin is latched during power-up or reset. PxMODE[3:0] defined P0MODE[2]/ 110

as:

P0RXER

0000=Auto-negotiation, advertise all capabilities, prefer MASTER.

P0MODE[1]/ 114 67

0001=Auto-negotiation, advertise all capabilities, prefer SLAVE.

P0COL

0010=Auto-negotiation, advertise only 100Base-TX half duplex.

P0MODE[0]/ 115 68

0011=Auto-negotiation, advertise only 100Base-TX full duplex.

P0CRS

0100=Reserved.

0101=Reserved.

P1MODE[3]/ 60 35

0110=Reserved.

P1RXDV

0111=Reserved.

P1MODE[2]/ 63 36

1000=Auto-negotiation, advertise only 1000Base-T full duplex,

P1RXER

force MASTER.

P1MODE[1]/ 37

1001=Auto-negotiation, advertise only 1000Base-T full duplex,

P1COL force SLAVE. P1MODE[0]/ 65 38 1010=Auto-negotiation, advertise only 1000Base-T full duplex, P1CRS prefer MASTER.

1011=Auto-negotiation, advertise only 1000Base-T full duplex, prefer SLAVE.

1100=Auto-negotiation, advertise all capabilities, force MASTER. 1101=Auto-negotiation, advertise all capabilities, force SLAVE. 1110=Auto-negotiation, advertise only 10Base-T half duplex. 1111=Auto-negotiation, advertise only 10Base-T full duplex.

54 TXDLY/ OPD GTXC Clock Delay Select. This pin enables GTXC input delay in

RGMII mode (see Table 22 for detailed configuration). P1RXD3

55 RXDLY/ OPD RXC Clock Delay Select. This pin enables RXC output delay in

RGMII mode (see Table 22 for detailed configuration). P1RXD2

62 106 OPD 1: Disable auto crossover detection DIS_AUTOX

OVER/ 0: Enable auto crossover detection P0RXD0

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 24 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.11. Miscellaneous Pins Table 12. Miscellaneous Pins

QFN76 Q128 Pin Name Type Description

Pin# Pin#

29 45 RESETB I Hardware Reset. Active low reset signal. To complete the reset function,

this pin must be asserted for at least 10ms. It must be pulled high for normal operation.

23 35 MDI_REF IB MDI Bias Resistor. Adjusts the reference current for both PHYs. A

resistor of 2.49KΩ±1% is connected between this pin and ground.

24 37 RTT1 O Test Pin 1. Reserved pin for internal analog debugging. Connect to

ground through a 1KΩ resistor. If debug is not important and there are board space constraints, this pin can be left floating.

25 38 RTT2 I Test Pin 2. Reserved pin for internal analog debugging. Connect to

ground through a 1KΩ resistor. If debug is not important and there are board space constrains, this pin can be left floating.

5 ATEST O Analog Test Pin. Reserved pin for internal analog debugging. Connect to

ground through a 1KΩ resistor. If debug is not important and there are board space constraints, this pin can be left floating.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 25 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 7.12. Power and Ground Pins Table 13. Power and Ground Pins

QFN76 Pin# 21, 26, 74 30, 66

QFP128 Pin# 4, 19 32, 39 46, 113

Pin Name

Type

Description

3.3V Power Supply

AVDD33 PWR Analog Power 3.3V. RVDD33

PWR Analog Power 3.3V for Internal Regulator.

1.8V Power Supply

AVDD18 PWR Analog Power 1.8V.

5, 10, 6, 12

15, 20 18, 25, 31

22 33 AVDDPLL PWR Analog Power 1.8V for PLL This pin is filtered with a low

resistance series ferrite bead and 1000pF + 2.2uF shunt capacitors to ground.

43 81 SVDD18 PWR Analog Power 1.8V for RSGMII.

1.2V Power Supply

27 40 AVDD12 PWR Analog Power 1.2V. 51 SVDD12 PWR Analog Power 1.2V for RSGMII. 31, 34, 39, 50, 58, 66, VDD12 PWR Digital Power 1.2V for Digital Core. 42, 53, 57, 74, 92, 99, 61, 65 105, 111

2.5V Power Output Pin

28, 33, 41, 44, 57, 71, VDDIO PWR Digital I/O Power 2.5V. This power is generated from an internal

regulator. Connect the following group of pins together 52, 60, 69 90, 103,

QFP-128:Group(44,57,71) ,Group(90,103,119) 119

QFN-76: Group(28,33,41),Group (52,60,69)

If MII/GMII/RGMII is not used, no external PCB trace is required. Only connect to ground through a decoupling capacitor. Ground

GND PAD 9, 15, 22, AVSS GND Analog ground.

28, 36, 43,

GND PAD 34 AVSSPLL GND PLL ground. GND PAD 53, 61, 67, VSS12 GND Digital Core ground.

77, 95, 100, 108, 112

GND PAD 47, 104 VSSIO GND Digital I/O ground.

46 84 SVSS18 PWR Analog 1.8V GND for RSGMII. 48 86 SVSS12 PWR Analog 1.2V GND for RSGMII.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 26 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8. Functional Description

8.1. MDI Interface The RTL8212/RTL8212N/8211N uses a single common MDI interface to support 10Base-T, 100Base-Tx, and 1000Base-T. This interface consists of four signal pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10/100 links and during auto-negotiation, only pairs A and B are used. Table 14 shows the mapping between the pairs and the RJ-45 signals.

Table 14. Mapping of Twisted-Pair Outputs to RJ-45 Connectors

Pairs A B C D

RJ-45 Connector

1 and 2 3 and 6 4 and 5 7 and 8

8.1.1. Crossover Detection and Auto Correction

The RTL8212/RTL8212N/8211N automatically determines whether or not it needs to crossover between pairs; removing the need for an external crossover cable. When connecting to a device that does not perform MDI crossover, the RTL8212/RTL8212N/RTL8211N automatically switches its pin pairs to communicate with the connecting device. When connecting to a device that does have MDI crossover capability, an algorithm determines which end performs the crossover function.

The crossover detection and auto correction function can be disabled by strap pin. The RTL8212/RTL8212N/8211N is set to MDI Crossover by default. The pin mapping in MDI and MDI Crossover mode is given in Table 15.

Table 15. Media Dependent Interface Pin Mapping

Pairs

MDI MDI Crossover

1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T

A A TX TX B RX RX B B RX RX A TX TX C C unused unused D unused Unused D D unused unused C unused unused 27

Track ID: JATR-1076-21 Rev. 1.2

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

RTL8212/RTL8212N/RTL8211N Datasheet 8.1.2. Polarity Correction

The RTL8212/RTL8212N/8211N automatically correct polarity errors on the receiver pairs in 10Base-T and 1000Base-T modes. In 100Base-Tx mode, the polarity is irrelevant.

In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle symbols. Once the descrambler is locked the polarity is also locked on all pairs. The polarity becomes unlocked only when the receiver loses lock.

In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The polarity becomes unlocked when the link is down.

+RX_+TX_+_TX_+ RX_+ Figure 7. Conceptual Example of Polarity Correction

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 28 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.1.3. MAC Interface

The RTL8212/RTL8212N/RTL8211N MAC interface supports GMII/MII, RGMII, and RSGMII (2.5Gbps serial interface; RTL8212N and RTL8211N only). The MAC interface selection is set by INTF_SEL[1..0]. Table 16 shows the data rates supported through each interface, and Table 17 shows each MAC interface operation mode.

Table 16. Data Rates Supported Through Each Interface

MAC Interface 10Base-T 100Base-TX 1000Base-T

GMII √ MII √ √ RGMII √ √ √

RSGMII (RTL8212N/RTL8211N only) √ √ √

Table 17. MAC Interface Modes of Operation

MAC Interface Speed Data Width Clock Frequency Clock Edge Notes

GMII 1000 8 bits 125MHz Rising 100 4 bits 25MHz Rising MII

10 4 bits 2.5MHz Rising 1000 4 bits 125MHz Rising/Falling RGMII 100 4 bits 25MHz Rising 1 10 4 bits 2.5MHz Rising 1 1000 1 bits 125MHz Rising 2 RSGMII

(RTL8212N/RTL8211N 100 1 bits 125MHz Rising 3 only) 10 1 bits 125MHz Rising 3 Note 1: The data may be duplicated on the falling edge of the appropriate clock when the interface operates at 10 and 100Mbps speeds.

Note 2: The internal PLL generates 20 sub-phase clock signals by dividing the 125MHz clock. The data can be latched on

the rising edge of each sub-phase signal. The data bandwidth of the RSGMII interface is up to 2.5Gbps (125M*20*1).

Note 3: Operation at 10 and 100Mbps uses respectively only 1% and 10% of the RSGMII Interface bandwidth.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 29 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.2. Gigabit Media Independent Interface (GMII/MII) Table 18 indicates the signal mapping of the RTL8212 to the Gigabit Media Independent Interface (GMII/MII). MII signaling to support 100Base-Tx and 10Base-T modes is implemented by sharing pins of the GMII interface. The interface supports GMII to copper connections at all three speeds. The GMII mode does not support carrier extension and packet concatenation in both the transmit and receive directions, due to no TXER pin.

Table 18. Gigabit Media Independent Interface

RTL8212 Pins GMII MII

GTXC GTX_CLK - TXC - TXC TXEN TX_EN TX_EN TXD[7..4] TXD[7..4] - TXD[3..0] TXD[3..0] TXD[3..0] RXC RX_CLK RX_CLK RXER RX_ER RX_ER RXDV RX_DV RX_DV RXD[7..4] RXD[7..4] - RXD[3..0] RXD[3..0] RXD[3..0] CRS CRS CRS COL COL COL

Figure 8. GMII Signal Diagram

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

30 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet In 1000Base-T operation, when GMII mode is selected, a 125MHz transmit clock is expected on GTXC, and RXC sources the 125MHz receive clock. At the same time, TXC sources 25MHz, 2.5MHz, or 0MHz depending on the MDI status.

In 10Base-T and 100Base-TX modes, when MII mode is selected, both TXC and RXC source 25MHz or 2.5MHz, respectively. TXD[3:0] and RXD[3:0] signals are used. GTXC and TXD[7..4] signals must be pulled high or low and must not be left floating. RXD[7..4] are driven low.

Figure 9. MII Signal Diagram

During the transition from one speed to another, a dead time of 1.5 clock cycles may occur in RXC and TXC (in order to ensure a glitch-free clock).

Note: The GMII and MII interfaces are enabled by hardware configuration bits INTF_SEL[1..0] that are latched at the end of hardware reset.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 31 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.2.1. Reduced GMII (RGMII)

The RTL8212 supports the RGMII Rev. 2.0 specification. This interface reduces the interconnection between the MAC and the PHY to 12 pins. In order to accomplish this objective, the data paths and all associated control signals are reduced. Control signals are multiplexed and both edges of the clock are used.

For Gigabit operation, the transmit and receive clocks operate at 125MHz. For 10/100 operation, the clocks operate at 2.5MHz or 25MHz respectively. Once the RGMII is selected in all three speeds, transmit control is presented on both clock edges of GTXC (TXC). Receive control (RX_CTL) is presented on both clock edges of RXC (RXC).

The RGMII interface is selected by setting INTF_SEL[1..0] to ‘10’.

Table 19. MAC Interface Modes of Operation

RTL8212 Pins

Description

125MH, 25MHz, or 2.5MHz transmit clock, with +/- 50 ppm tolerance,

GTXC TXC based on the selected speed.

Transmit Control Signals. TX_EN is encoded on the rising edge of GTXC. TXEN TX_CTL TX_ER XOR TX_EN is encoded on the falling edge of GTXC.

Transmit data. In 1000Base-T mode, bits 3:0 are presented on the rising edge of GTXC, and bits 7:4 is presented on the falling edge of GTXC.

TXD[3..0] TD[3..0] In 10/100 mode, bits 3:0 is presented on the rising edge of GTXC, and duplicated on the falling edge of GTXC.

125MH, 25MHz, or 2.5MHz receive clock, with +/- 50 ppm tolerance,

RXC RXC based on the selected speed.

Receive Control Signals. RX_DV is encoded on the rising edge of

RXDV RX_CTL RXC, RX_ER XOR RX_DV is encoded on the falling edge of RXC. Receive data. In 1000Base-T mode, bits 3:0 is presented on the rising edge of RXC, and bits 7:4 are presented on the falling edge of RXC.

RXD[3..0] RD[3..0] In 10/100 mode, bits 3:0 is presented on the rising edge of RXC, and duplicated on the falling edge of RXC.

RGMII

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 32 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet

Figure 10. RGMII Signal Diagram

8.2.2. 10/100 Functionality

This interface can be used to implement the 10/100Mbps Ethernet Media Independent Interface (MII) by reducing the clock rate to 25MHz for 100Mbps operation and 2.5MHz for 10Mbps. The TXC will always be generated by the MAC and RXC will always be generated by the PHY. During packet reception, the RXC may be stretched on either the positive or negative pulse to accommodate the transition from the free running clock to a data-synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or negative pulses is allowed. No glitch of the clocks are allowed during speed transitions.

The interface will operate at 10 and 100Mbps speeds exactly the same way it does at Gigabit speed with the exception that the data may be duplicated on the falling edge of the appropriate clock.

The MAC must hold TXEN (TX_CTL) low until the MAC has ensured that TXEN (TX_CTL) is operating at the same speed as the PHY.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 33 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.2.3. TX_CTL and RX_CTL Coding

To reduce power consumption of this interface, TX_ER and RX_ER are encoded in a manner that minimizes transitions during normal network operation. This is done via the following encoding method. Note that the RTL8212 does not support Half-Duplex in 1000Base-T and the GMII_TX_ER signal is tied to logic low at all times, carrier extend and transmit errors never appear at the transmitting and receiving end.

TX_CTL Í GMII_TX_ER (XOR) GMII_TX_EN RX_CTL Í GMII_RX_ER (XOR) GMII_RX_DV

While receiving a valid frame with no errors, RX_DV=true is generated as a logic high on the rising edge of RXC, and RX_ER=false is generated as a logic high on the falling edge of RXC. When no frame is being received, RX_DV=false is generated as a logic low on the rising edge of RXC, and RX_ER=false is generated as a logic low on the falling edge of RXC.

When receiving a valid frame with errors, RX_DV=true is generated as a logic high on the rising edge of RXC, and RX_ER=true is generated as a logic low on the falling edge of RXC.

During normal frame transmission, the signal stays at high for both edges of TXC. During normal inter-frame, the signal stays low for both edges.

Table 20. TX_ER and TX_EN Encoding

TX_CTL 0, 0 1, 1

GMII_TX_EN

0 1

GMII_TX_ER

0 0

Description

Normal inter-frame

Normal data transmission

Note: As GMII_TX_ER is always tied to logic low in the RTL8212, no transmit error symbol or carrier extend symbol occurs in data transmission.

Figure 11. RGMII Data Transmission

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

34 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet Table 21. RX_ER and RX_DV Encoding

RX_CTL GMII_RX_DV GMII_RX_ER Description 0, 0 0 0 Normal inter-frame 0, 1 0 1 Carrier sense 1, 1 1 0 Normal data reception 1, 0 1 1 Data reception error

Note 1: The MAC is designed to acquire the link status, speed and duplex mode of the PHY via MDC/MDIO polling, so

the RTL821 does not implement specific code onto RXD[3..0] to inform MAC of the PHY status during normal inter-frame.

Note 2: In addition to the encoding of RX_DV and RX_ER as indicated in Table 21, a value of ‘FF’ also exists on the

RXD[7..0] simultaneously when the Carrier Sense symbol occurs.

Figure 12. RGMII Data Reception Without Error

Figure 13. RGMII Data Reception With Error

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 35 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.2.4.

• •

In-Band Status

RX_DV is true

Where RX_DV is false, RX_ER is true, and a value of ‘FF’ exists on the RXD[7..0] bits simultaneously

CRS is indicated where:

Carrier Extend and Carrier Extend Error are not supported by the RTL8212. Collision is determined at the MAC by the assertion of TXEN being true while either CRS or RXDV are true. The PHY will not assert CRS as a result of TXEN being true.

8.2.5. Four RGMII Modes

The RTL8212 supports four different timing modes of operation. Hardware strapping pins TXDLY and RXDLY can be used to select between the four RGMII timing modes. Refer to Table 44, page 58, for RGMII Mode timing.

Each bit adjusts the delay of data with respect to clock edges. For both inputs and outputs of the PHY the data can change either simultaneously with the clock edges, or the data can have setup and hold with respect to clock edges.

Table 22. RGMII Timing Modes

Mode Mode 0

Mode 1 Mode 2 Mode 3

TXDLY 0 0 1 1

RXDLY 0 1 0 1

PHY Input GTXC vs. data Meet setup and hold time Meet setup and hold time Simultaneous with clock edge Simultaneous with clock edge

PHY Output RXC vs. data

Simultaneous with clock edge Meet setup and hold time Simultaneous with clock edge Meet setup and hold time

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 36 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.3. Reduced Serial GMII (RTL8212N & RTL8211N Only) To reduce PCB complexity and IC pin count, Realtek offers a proprietary interface; the Realtek Reduced Serial Gigabit Media Independent Interface (RSGMII). This innovative 2.5Gbps serial interface provides an upto 5 inch long MAC to PHY communication path. The RSGMII can carry the full duplex gigabit Ethernet data streams of two ports simultaneously, and recover clock from the data rather than use a dedicated clock. The RSGMII reduces the interconnection between the gigabit Ethernet PHY and MAC to only 4 pins. Figure 14 depicts the RSGMII interconnection.

MACPort0TXTXPHYPort0RSGMIIRSGMIIRXPort1RXPort1 Figure 14. RSGMII Interconnection Diagram

The RSGMII interface runs at 2.5Gbps in 10M/100M/1000Mbps modes. Clearly, a 2.5Gbps data rate is

excessive for interfaces operating at 10M/100Mbps. When operating in these conditions, the interface elongates each byte of data by 10 times for 100Mbps, and by 100 times for 10Mbps, through a rate adaptation block.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 37 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet The data paths and all associated control signals are transmitted from each port and recovered at the receiver side via proprietary transmission encode/decode and Serial/De-serial translation.

Taking the Realtek RTL8369 and RTL8212N as examples (see Figure 15), the RTL8369 contains four RSGMII (4 pairs) and the RTL8212N contains one RSGMII (1 pair). The RTL8369 generates SnTX+/-, n=0-3 signals to four RTL8212N’s, and receives SnRX+/-, n=0-3 signals from four RTL8212N’s. Each RSGMII carries two gigabits of Ethernet data from PHY to MAC and MAC to PHY.

In traditional GMII applications, the MAC to PHY interface requires at least 20 pins to carry 1 port’s bi-directional gigabit Ethernet traffic. A MAC to PHY RSGMII needs only 4 pins to carry two port’s gigabit Ethernet traffic. This greatly improves PCB layout size and complexity in gigabit switch design.

Figure 15. Realtek 8G Switch Application with RSGMII

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 38 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.3.1. RSGMII Data Transfer

At the receive side, GMII signals of the two gigabit Ethernet PHY ports enter at 10/100/1000Mbps, clocked at 2.5/25/125MHz. Each port passes these signals through Ethernet PHY receive rate adaptation to output data RXD[7..0] in the 125MHz clock domain. Both RXD are then sent to the individual PCS Transmit State Machine to generate proprietary encoded code-words A and B. The PHY combines the code-words A and B generated from the two ports to a code-word C, and converts it to a serial (bit by bit) stream for the Ethernet MAC at a 2.5Gbps data rate.

At the transmit side, the PHY de-serializes data to recover the encoded code-word C. Next the synchronization block checks the code-word C to determine the synchronization status between links, and to realign if it detects a loss of synchronization.

The Ethernet PHY separates the synchronous code-word C, into A and B for each port. Each port’s code-word is then recovered to the GMII signal in the 125MHz clock domain by passing through individual PCS Receive State Machines. Both the decoded GMII signals have to pass the PHY Transmit Rate Adaptation block to output data segments according to the port speed. The transmitting and receiving operation flow on the Ethernet MAC side is the same as the Ethernet PHY side. Figure 16 and Figure 17 show the functional block diagram at the PHY and MAC side respectively. They illustrate how the PCS layer is modified and incorporated at the PHY and MAC side within the RSGMII interface.

code-word APort1Port0PCS TransmitStateMachineP1RX_DVP1RX_ERP1RXD[7..0]P1RX_CLK125MHzP0RX_DVP0RX_ERP0RXD[7..0]P0RX_CLK125MHzPort1Port0PHY ReceiveRateAdaptationGMII Signals from port1P1RX_CLK2.5/25/125MHzGMII Signals from port0P0RX_CLK2.5/25/125MHzRXSerializercode-word Ccode-word Bcode-word ATXDe-Serializercode-word CPort1Port0Port0PCS ReceiveStateMachineP1TX_ENP1TX_ERP1TXD[7..0]P1TX_CLK125MHzP0TX_DVP0TX_ERP0TXD[7..0]P0TX_CLK125MHzPort1Port0PHY TransmitRateAdaptationGMII Signals from port1P1TX_CLK2.5/25/125MHzGMII Signals from port0P0TX_CLK2.5/25/125MHzSynchro-nizationcode-word B

Figure 16. RSGMII Functional Block Diagram at Ethernet PHY Side

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

39 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet

Figure 17. RSGMII Functional Block Diagram at Ethernet MAC Side

8.4. MDC/MDIO Management Interface The RTL8212/RTL8212N/RTL8211N support the IEEE compliant Management Data Input/Output (MDIO) Interface. This is the only method for the MAC to acquire the PHY statuses. The MII management interface registers are written and read serially, using the MDC/MDIO pins. Data transferred to and from the MDIO pins is synchronized with the MDC clock. All transfers are initiated by the MAC. A clock of up to 12.5MHz must drive the MDC pin of the RTL8212/RTL8212N/RTL8211N.

The MDIO frame structure starts with a 32-bit preamble, which is required by the RTL8212/8211. Following bits include a start-of-frame marker, an op-code, a 10-bit address field, and a 16-bit data field. The address field is divided into two 5-bit segments. The first segment identifies the PHY address and the second identifies the register being accessed.

The four uppermost bits of the 5-bit PHY address are determined by the hardware strapping values during power up. The LSB of the PHY address is ‘0’ for Port0 and ‘1’ for Port1. The MDIO protocol provides both read and write operations. During a write operation, the MAC drives the MDIO line for the entire

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

40 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet frame. For a read operation, a turn-around time is inserted in the frame to allow the PHY to drive back to the MAC. The MDIO pin of the MAC must be put in a high-impedance during these bit times. Figure 18 and Figure 19, page 41 depict the MDIO read and write frame format respectively.

8.4.1. Preamble Suppression

The RTL8212/RTL8212N/RTL8211N is permanently programmed for preamble suppression. A preamble of 32 bits is required only for the first read or write. The management preamble may be as short as 1 bit.

Figure 18. MDIO Read Frame Format

Figure 19. MDIO Write Frame Format

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 41 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.5. Hardware Configuration Interface The RTL8212/RTL8212N is a dual-port device. The RTL8211N is a single-port device. Configuration options like MAC interface, physical address, PHY operating mode are configured by using the configuration pins. These pins are shared with GMII/RGMII receive pins. Except for the PHY operating mode, both ports may be configured independently. Settings are implemented simultaneously after power-on reset. Table 23 shows the configuration definitions.

Table 23. Configuration Pin Definitions

Configuration

Description

Interface Select: INTF_SEL[1:0] specifies the MAC interface operating mode for both ports. 00=RSGMII 01=GMII/MII 10=RGMII 11=Reserved

PHY Address: PHYADR[4:1] sets the uppermost 4 bits of the 5-bit PHY address upon reset. The LSB is ‘0’ for Port 0 and ‘1’for Port1.

Serial LED Mode Select: LEDMODE specifies the serial LED display mode for both ports. There are two LED display modes in the RTL8212/8211. 0=Mode 0 1=Mode 1

GTXCLK Clock Delay Select: GTXCLK determines the GTXCLK input delay in RGMII mode.

0=Output data may change simultaneously with the GTXCLK edges

1=Output data can have setup time and hold time with respect to GTXCLK edges

RXCLK Clock Delay Select: RXCLK determines the RXCLK output delay in RGMII mode. 0=Output data may change simultaneously with the RXCLK edges

1=Output data can have setup time and hold time with respect to RXCLK edges

INTF_SEL[1:0]

PHYADR[4:1]

LEDMODE

GTXCLK

RXCLK

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 42 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.6. LED Configuration The RTL8212/RTL8212N/RTL8211N supports serial LED status streams for LED display. The forms of LED status streams are controlled by LEDMODE pins (see Table 24) which are latched upon reset. All LED statuses are represented as active-low.

Table 24. LED Mode

LED Mode

0 1

Output Sequences

Dup/Col, Link/Act, Spd1000, Spd100

Dup/Col, Spd1000/Act, (Spd100,Spd10)/Act

Table 25. LED Status

LED Status

Col/Fulldup Link/Act Spd1000 Spd1000/Act (Spd100,Spd10)/Act

Description

Collision, Full duplex Indicator. Blinks every 43ms when collision occurs. Low for full duplex, and high for half duplex mode.

Link, Activity Indicator. Low for link established. Blinks every 43ms when the corresponding port is transmitting or receiving.

1000Mbps Speed Indicator. Low for 1000Mbps.

1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinks every 43ms when the corresponding port is transmitting or receiving.

10/100Mbps, Speed/Activity Indicator. Low for 10/100Mbps. Blinks every 43ms when the corresponding port is transmitting or receiving.

8.6.1.

• • • •

LED System Application Examples

4 single-color LEDs: Link/Act, Spd1000, Spd100, Dup/Col (set LEDMODE=0) 3 single-color LEDs: Link/Act, Spd1000, Spd100 (set LEDMODE=0)

2 single-color, 1 bi-color LEDs: Link/Act, Dup/Col, Spd1000/Spd100 (set LEDMODE=0) 1 single-color, 1 bi-color LED: Dup/Col, Spd100/Spd10/100/Act (set LEDMODE=1)

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 43 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.6.2. Serial Stream Order

Every bit stream is output port by port, from port0 to port1 with Col/Fulldup as the first bit in a port stream.

Table 26. Serial Stream Order (Mode 0)

0 1 2 3 4 5 6 7 Port 0 Port 0 Port 0 Port 0 Port 1 Port 1 Port 1 Port 1 Dup/Col Link/Act Spd1000 Spd100 Dup/Col Link/Act Spd1000 Spd100

741 Pin H G F E D C B A Clock Mode 0

Table 27. Serial Stream Order (Mode 1)

Clock Mode 1 741 Pin

- -

- -

0

Port 0 Dup/Col

1 2 3 4 5 Port 0 Port 0 Port 1 Port 1 Port 1 Spd1000/Act Spd100/Act Dup/Col Spd1000/Act Spd100/Act

F E D C B A H G

8.7. System Clock Interface Figure 20. Clock Generated from MAC (RSGMII Mode)

Note: When CLKIN is used, pull the X1 pin low to GND.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 44 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8. Register Descriptions The first six registers of the MII are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp. for internal use and are reserved for specific uses.

8.8.1.

RO: RW: LL:

Register Symbols

Read Only Read/Write

Latch Low until cleared

LH: SC:

Latch High until cleared Self Clearing

8.8.2. MII Specification Defined Registers

Table 28. MII Specification Defined Registers

Register Description

0 Control Register. 1 Status Register. 2 PHY Identifier 1 Register. 3 PHY Identifier 2 Register. 4 Auto-Negotiation Advertisement Register. 5 Auto-Negotiation Link Partner Ability Register. 6 Auto-Negotiation Expansion Register. 7 Auto-Negotiation Page Transmit Register. 8 Auto-Negotiation Link Partner Next Page Register. 9 1000Base-T Control Register. 10 1000Base-T Status Register. 15 Extended Status.

Default

0x1140 0x7949 0x001C 0xC912

0x01E1 0x0000

0x0000 0x2001 0x0000 0x0F00 0x0000

0x3000

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 45 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.3. Register0: Control

Table 29. Register0: Control

Description

Mode Default

RW/SC 0 1PHY reset 0=Normal operation This bit is self-clearing.

0.14 Loopback This will loopback TXD to RXD and ignore all activity on

the cable media. 1=Enable loopback 0=Normal operation

0.13 Speed Selection[0] [0.6,0.13] Speed Selection[1:0].

11=Reserved 10=1000 Mbps 01=100 Mbps 00=10 Mbps

Note: The SMI: Serial Management Interface which is

composed of MDC, MDIO, allows the MAC to manage the PHY.

0.12 Auto Negotiation This bit can be set through SMI (Read/Write).

Enable 1=Enable Auto-negotiation process

0=Disable Auto-negotiation process

0.11 Power Down 1=Power down. All functions will be disabled except SMI

read/write function 0=Normal operation

0.10 Isolate 1=Electrically isolates the PHY from

MII/GMII/RGMII/RSGMII.

PHY is still able to respond to MDC/MDIO =0=Normal operation

0.9 Restart Auto 1=Restart Auto-Negotiation process

Negotiation 0=Normal operation

0.8 Duplex Mode 1=Full duplex operation

0=Half duplex operation

When Auto-Negotiation is enabled, this bit reflects the result of Auto-Negotiation (Read Only).

When Auto-Negotiation is disabled, this bit can be configured through SMI (Read/Write).

0.7 Collision Test 1=Collision test enabled

0=Normal operation

When set, this bit will cause the COL signal to be asserted in response to the assertion of TXEN within 512-bit times. The COL signal will be de-asserted within 4-bit times in response to the de-assertion of TXEN.

0.6 Speed Selection[1] See bit 13. 0.[5:0] Reserved

Bit(s) Name 0.15 Reset RW 0 RW 0 RW 1 RW 0 RW 0 RW/SC 0 RW 1 RO 0 RW RO 1 0

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

46 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.4. Register1: Status

Table 30. Register1: Status

Bit(s) Name

1.15 100Base-T4 Description Mode Default 0No 100Base-T4 capability RO 0 The RTL8212/RTL8212N/RTL8211N does not support 100Base-T4 mode. This bit should always be 0.

1.14 100Base-X Full Duplex 1=100Base-X full duplex capable RO 1 0=Not 100Base-X full duplex capable

1.13 100Base-X Half Duplex 1=100Base-X half duplex capable RO 1 0=Not 100Base-X half duplex capable

1.12 10Mbps Full Duplex 1=10Mbps full duplex capable RO 1 0=Not 10Mbps full duplex capable

1.11 10Mbps Half Duplex 1=10Mbps half duplex capable RO 1 0=Not 10Mbps half duplex capable

1.10 100Base-T2 Full Duplex 0=No 100Base-T2 full duplex capability. RO 0 The RTL8212/RTL8212N/RTL8211N does not support 100Base-T2 mode. This bit should always be 0.

1.9 100Base-T2 Half Duplex 0=No 100Base-T2 half duplex capability RO 0 The RTL8212/RTL8212N/RTL8211N does not support 100Base-T2 mode. This bit should always be 0.

1.8 Extended Status 1=Extended status information in Register 15 RO 1 The RTL8212/RTL8212N/RTL8211N always supports Extended Status Register.

1.7 Reserved Reserved. RO 0 1.6 RO 1 MF Preamble The RTL8212/RTL8212N/RTL8211N will accept

Suppression management frames with preamble suppressed.

1.5 1=Auto-negotiation process completed. RO 0 Auto-negotiate =

Complete 0=Auto-negotiation process not completed.

1.4 Remote Fault RO/LH 0 1=Remote fault indication from link partner has been

detected.

0=No remote fault indication detected.

This bit will remain set until it is cleared by reading register 1 via management interface.

1.3 Auto-Negotiation Ability 1=Auto-negotiation capable (permanently =1) RO 1 0=Without Auto-negotiation capability.

1.2 Link Status 1=Link has never failed since previous read RO/LL 0 0=Link has failed since previous read

If link fails, this bit will be set to 0 until bit is read.

1.1 Jabber Detect 1=Jabber detected RO/LH 0 0=No Jabber detected

Jabber is supported only in 10Base-T mode.

1.0 Extended Capability 1=Extended register capable. (permanently =1) RO 1 0=Not extended register capable

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

47 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.5. Register2: PHY Identifier 1 Register

The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.

Table 31. Register2: PHY Identifier 1 Register

Reg. bit Name 2.[15:0] OUI Description

Composed of the 3rd to 18th bits of the Organizationally Unique Identifier (OUI), respectively.

Mode Default RO 001C h

8.8.6.

Reg. bit

3.[15:10] 3.[9:4] 3.[3:0]

Register3: PHY Identifier 2 Register

Table 32. Register3: PHY Identifier 2 Register

Name OUI

Model Number Revision Number

Description

Assigned to the 19th through 24th bits of the OUI. Manufacturer’s model number. Manufacturer’s revision number.

Mode RO RO RO

Default 110010 010001 0010

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 48 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.7. Register4: Auto-Negotiation Advertisement

This register contains the advertisement abilities of this device as they will be transmitted to its Link Partner during Auto-negotiation.

Table 33. Register4: Auto-Negotiation Advertisement

Description

1=Additional next pages exchange desired 0=No additional next pages exchange desired

=4.14 Reserved Permanently 0

4.13 Remote Fault 1=Set remote fault bit

0=Do not set remote fault bit

4.12 Reserved For future technology 4.11 Asymmetric Pause 1=Advertises that the RTL8212/RTL8212N/RTL8211N has

asymmetric flow control capability

0=No asymmetric flow control capability =4.10 Pause 1=Advertises that the RTL8212/RTL8212N/RTL8211N has flow control capability.

0= No flow control capability.

4.9 100Base-T4 1100Base-T4 capable

0=Not 100Base-T4 capable (Permanently =0)

4.8 100Base-TX-FD 1=100Base-TX full duplex capable

0=Not 100Base-TX full duplex capable

=4.7 100Base-TX 1=100Base-TX half duplex capable

0=Not 100Base-TX half duplex capable

4.6 10Base-T-FD 1=10Base-TX full duplex capable

0=Not 10Base-TX full duplex capable

4.5 10Base-T 1=10Base-TX half duplex capable

0=Not 10Base-TX half duplex capable

4.[4:0] Selector Field [00001]IEEE802.3

Note 1: The setting of Register 4 has no effect unless auto-negotiation is restarted or link down. Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted. Reg. bit 4.15

Name Next Page

Mode Default

RW 0 RO 0 RW 0 RW 0

RW 0 RW 0 RO 0 RW 1 RW 1 RW 1 RW 1 RO 00000

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 49 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.8. Register5: Auto-Negotiation Link Partner Ability

This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after a successful Auto-negotiation.

Table 34. Register5: Auto-Negotiation Link Partner Ability

Reg. bit

5.15 5.14 5.13

Name Next Page Acknowledge Remote Fault

Description =1=Link partner desires Next Page transfer

0=Link partner does not desire Next Page transfer 1=Link Partner acknowledges reception of FLP words 0=No acknowledgement by Link Partner 1=Remote Fault indicated by Link Partner 0=No remote fault indicated by Link Partner Reserved.

1=Asymmetric Flow control supported by Link Partner 0=No Asymmetric flow control supported by Link Partner When auto-negotiation is enabled, this bit reflects Link Partner ability. (read only).

1=Flow control supported by Link Partner 0=No flow control supported by Link Partner

When auto-negotiation is enabled, this bit reflects Link Partner ability. (read only)

1=100Base-T4 supported by Link Partner 0=100Base-T4 not supported by Link Partner

1=100Base-TX full duplex supported by Link Partner 0=100Base-TX full duplex not supported by Link Partner 1=100Base-TX half duplex supported by Link Partner 0=100Base-TX half duplex not supported by Link Partner 1=10Base-TX full duplex supported by Link Partner 0=10Base-TX full duplex not supported by Link Partner 1=10Base-TX half duplex supported by Link Partner 0=10Base-TX half duplex not supported by Link Partner [00001]IEEE802.3

[00000]=No Information from Link Partner

Mode Default

RO 0 RO 0 RO 0 RO 0 RW 0 5.12 Reserved 5.11 Asymmetric Pause

5.10 Pause RO 0 5.9 5.8 5.7 5.6 5.5

100Base-T4 100Base-TX-FD 100Base-TX 10Base-T-FD 10Base-T

RO 0 RO 0 RO 0 RO 0 RO 0 RO 00000 5.[4:0] Selector Field

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 50 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.9. Register6: Auto-Negotiation Expansion

Table 35. Register6: Auto-Negotiation Expansion

Description

1=A fault has been detected via the Parallel Detection function

0=No fault has been detected via the Parallel Detection function

1=Link Partner is Next Page able 0=Link Partner is not Next Page able

1= RTL8212/RTL8212N/RTL8211N is Next Page able (permanently=1)

1=A New Page has been received 0=A New Page has not been received

If Auto-Negotiation is enabled, this bit means: 1=Link Partner is Auto-Negotiation able 0=Link Partner is not Auto-Negotiation able

Mode Default RO 0

RO 0 Reg. bit Name

6.[15:5] Reserved 6.4 Parallel Detection

Fault

6.3 6.2 6.1 6.0

Link Partner Next Page Ability Local Next Page Ability

Page Received Link Partner

Auto-Negotiation Ability

RO 0 RO 1 RO/LH 0 RO 0

8.8.10.

Reg. bit 7.15

Register7: Auto-Negotiation Page Transmit Register

Table 36. Register7: Auto-Negotiation Page Transmit Register

Name Next Page

Mode Default

RW 0 RO 0 RW 1

RW 0 Description

1=Another next page desired 0=No next page to send

7.14 Reserved 7.13 Message Page 1=Message page 7.12 Acknowledge 2 1=Local device has the ability to comply with the message

received

0=Local device has no ability to comply with the message received

7.11 Toggle Toggle bit. 7.10:0 Message/Unformatted Content of message/unformatted page.

Field

RO 0 RW 0x001

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 51 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.11. Register8: Auto-Negotiation Link Partner Next Page Register

Table 37. Register8: Auto-Negotiation Link Partner Next Page Register

Mode

RO RO RO RO RO RO

Default 0 0 0 0 0 0x000

Reg. bit Name Description 8.15 Next Page Received link code word bit 15. 8.14 Acknowledge Received link code word bit 14. 8.13 Message Page Received link code word bit 13. 8.12 Acknowledge 2 Received link code word bit 12.

=Received 8.11 Toggle link code word bit 11.

8.10:0 Message/Unformatted Received link code word bit 10:0.

Field

8.8.12.

Reg. bit 9.15:13

Register9: 1000Base-T Control Register

Table 38. Register9: 1000Base-T Control Register

Name Test Mode

Mode Default

RW 000 Description Test mode select: 000=Normal mode

001=Test mode 1 – Transmit waveform test

010=Test mode 2 – Transmit jitter test in MASTER mode 011=Test mode 3 – Transmit jitter test in SLAVE mode 100=Test mode 4 – Transmitter distortion test 101, 110, 111=Reserved

9.12 MASTER/SLAVE 1=Enable MASTER/SLAVE manual configuration

0=Disable MASTER/SLAVE manual configuration Manual

Configuration Enable

9.11 MASTER/SLAVE 1=Configure PHY as MASTER during MASTER/SLAVE

Configuration Value negotiation, only when 9.12 is set to logical one

0=Configure PHY as SLAVE during MASTER/SLAVE negotiation, only when 9.12 is set to logical one

9.10 Port Type 1Multi-port device

0=Single-port device

9.9 1000Base-T 1=Advertise PHY is 1000Base-T full duplex capable

Full Duplex 0=Advertise PHY is not 1000Base-T full duplex capable

9.8 1000Base-T 1=Advertise PHY is 1000Base-T half duplex capable

Half Duplex 0=Advertise PHY is not 1000Base-T half duplex capable

9.7:0 Reserved Reserved.

RW 0 RW 1 RW 1 RW 1 RW 0 RW 0

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 52 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 8.8.13. Register10: 1000Base-T Status Register

Table 39. Register10: 1000Base-T Status Register

Mode Default

RO 0 RO 0 Reg. bit Name Description

10.15 MASTER/SLAVE 1=MASTER/SLAVE configuration fault detected

Configuration Fault 0=No MASTER/SLAVE configuration fault detected

10.14 MASTER/SLAVE 1=Local PHY configuration resolved to MASTER

Configuration Fault 0=Local PHY configuration resolved to SLAVE Resolution

10.13 Local Receiver Status 1Local receiver OK

0=Local receiver not OK

10.12 Remote Receiver 1=Remote receiver OK

Status 0=Remote receiver not OK

10.11 Link Partner 1=Link partner is capable of 1000Base-T full duplex

1000Base-T 0=Link partner is not capable of 1000Base-T full duplex Full Duplex

10.10 Link Partner 1=Link partner is capable of 1000Base-T half duplex

1000Base-T 0=Link partner is not capable of 1000Base-T half duplex Half Duplex

10.9:8 Reserved Reserved 10.7:0 Idle Error Count Idle error counter. The counter stops automatically when it

reaches 0xFF

RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

=

8.8.14.

Reg. bit 15.15

Register15: Extended Status

Table 40. Register15: Extended Status Description

0=1000Base-X full duplex not capable 0=1000Base-X half duplex not capable 1=1000Base-T full duplex capable 0=1000Base-T half duplex not capable Reserved

Mode RO RO RO RO RO Default 0 0 1 0 0

Name

1000Base-X Full Duplex

15.14 1000Base-X Half

Duplex

15.13 1000Base-T Full

Duplex

15.12 1000Base-T Half

Duplex

15.11:0 Reserved

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 53 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 9. Characteristics

9.1. Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability may be affected. All voltages are specified reference to GND unless otherwise specified.

Table 41. Absolute Maximum Ratings

Parameter

Storage Temperature

Supply Voltage Referenced to VSS12 ,AVSS, AVSSPLL: VDD12, AVDD12, SVDD12 and AVDDPLL

Supply Voltage Referenced to AVSS: AVDD18 and SVDD18

Supply Voltage Referenced to AVSS: AVDD33 and RVDD33

Digital Input Voltage DC Output Voltage

Units °C

GND-0.5 +1.32 V Min -55

Max +150

GND-0.5 +1.98 GND-0.5 +3.63 GND-0.5 GND-0.5

VDDD VDDD

V V V V

9.2. Operating Range Table 42. Operating Range

Parameter

Ambient Operating Temperature (Ta)

1.2V VDDD, VDDA, and VDDIO Supply Voltage Range

1.8V VDDD, VDDA, and VDDIO Supply Voltage Range

3.3V VDDIO Supply Voltage Range

Units °C

1.14 1.26 V 1.71 1. V 3.14

3.46

V

Min 0

Max +65

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver 54 Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 9.3. DC Characteristics Table 43. DC Characteristics

Parameter

Power Supply Current for Analog 1.2V

SYM Condition Icc 10Base-T, Idle

10Base-T, Peak continuous 100% utilization 100Base-TX, Idle

100Base-TX, Peak continuous 100% utilization

1000Base-T, Idle

1000Base-T, Peak continuous 100% utilization Power saving Icc 10Base-T, Idle

10Base-T, Peak continuous 100% utilization 100Base-TX, Idle

100Base-TX, Peak continuous 100% utilization

1000Base-T, Idle

1000Base-T, Peak continuous 100% utilization Power saving Icc 10Base-T, Idle

10Base-T, Peak continuous 100% utilization 100Base-TX, Idle

100Base-TX, Peak continuous 100% utilization

1000Base-T, Idle

1000Base-T, Peak continuous 100% utilization Power saving Icc 10Base-T, Idle

10Base-T, Peak continuous 100% utilization 100Base-TX, Idle

100Base-TX, Peak continuous 100% utilization

1000Base-T, Idle

1000Base-T, Peak continuous 100% utilization Power saving

Min 40 40 40 40 40 40 40 15 15 15 105 105 450 470 15 5 5 90 90 190 190 5 60 230 50 50 110 110 40

Typical 45 45 45 45 45 45 45 20 20 20 110 110 460 480 20 10 10 100 100 200 200 10 70 240 60 60 120 120 50

Max 50 50 50 50 50 50 50 30 30 30 120 120 480 500 30 15 15 110 110 210 210 15 80 250 70 70 150 150 60

Units mA

Power Supply Current for Digital 1.2V

mA

Power Supply Current for Analog 1.8V

mA

Power Supply Current for Analog 3.3V

mA

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RTL8212/RTL8212N/RTL8211N Datasheet Parameter Total Power

Consumption for all ports

SYM Condition PS 10Base-T, Idle

10Base-T, Peak continuous 100% utilization 100Base-TX, Idle

100Base-TX,Peak continuous 100% utilization

1000Base-T, Idle

1000Base-T, Peak continuous 100% utilization Power saving

TTL Input High Voltage Vih TTL Input Low Voltage TTL Input Current TTL Input Capacitance Output High Voltage Output Low voltage Output Three State Leakage Current

Vil Iin Cin Voh Vol |IOZ|

Min 273 834 393 501 1293 1317 207 2.0 - -10 - 2.2 0.0 -

Typical 327 888 456 5 1362 1386 261 - - - 3 - - -

Max 387 948 525 633 1509 1533 321 - 0.8 10 - 2.8 0.4 10

Units mW

V V uA pF V V µA

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RTL8212/RTL8212N/RTL8211N Datasheet 9.4. AC Characteristics MRXC/PTXC, MDC

MRXD/PTXD[3: 0], MRXDV/PTXEN, MCOL, MDIOTsTh

Figure 21. MII Interface Reception Data Timing

MRXC/PTXC, MDC

TcycMRXD/PTXD[3: 0], MRXDV/PTXEN, MCOL, MDIOTosToh

Figure 22. MII Interface Transmission Data Timing

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RTL8212/RTL8212N/RTL8211N Datasheet

Table 44. Digital Timing Characteristics

Parameter

100BaseT RXC, TXC 10BaseT

RXC, TXC,

RXD[3:0], RXDV, PCOL, Output Setup time

RXD[3:0], RXDV,

COL, Output Hold time TXD[3:0], TXEN, Setup time

TXD[3:0], TXEN, Hold time RXC

RXD[7:0],RXDV, COL Output Setup time

RXD[7:0], RXDV, COL Output Hold time RXC

RXD[3:0],RXCTL Output Setup time (When RXDLY=1) RXD[3:0], RXCTL Output Hold time (When RXDLY=1) RGMII Signal Rising Time

RGMII Signal Rising Time LED On Time LED Off Time

SYM Condition Tcyc Tcyc Tos

MII Mode Timing

RXC, TXC clock cycle time RXC, TXC clock cycle time

Output Setup time from RXC rising edge to RXD[3:0], RXDV, COL

Output Hold time from RXC rising edge to RXD[3:0], RXDV, COL

TXD[3:0], TXEN to TXC rising edge setup time

TXD[3:0], TXEN to TXC rising edge hold time

GMII Mode Timing

RXC clock cycle time

Output Setup time from RXC rising edge to RXD[0..7], RXDV, COL

Output Hold time from RXC rising edge to RXD[0..7], RXDV, COL

RGMII Mode Timing

RXC clock cycle time

Output Setup time from RXC rising/falling edge to RXD[0..3], RXCTL

Output Hold time from RXC rising/falling edge to RXD[0..3], RXCTL

RGMII Signals 20% to 80% rising time RGMII Signals 80% to 20% falling time

I/O Min O O O

21

Typ 40±50 ppm 400±50 ppm 23

Max 25

Units ns ns ns

Toh Ts Th

O I I

13 4 2

15

18

ns ns ns

Tcyc Tos Toh

O O O

5.4 0.9

100±50 ppm 6.6 1.2

- -

ns ns ns

Tcyc Tos

O O 100±50 ppm

1.35 1.6

1.8

ns ns

Toh O 2.2 2.4 2.7 ns

Tr Tf

O O

0.750.75

ns ns

LED Timing

tLED While LED blinking on

tLED While LED blinking off

O O

43 43

ms ms

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RTL8212/RTL8212N/RTL8211N Datasheet 10. Design and Layout Guide

In order to achieve maximum performance using the RTL8212/RTL8212N/RTL8211N, good design attention is required throughout the design and layout process. The following are some recommendations on how to implement a high performance system.

10.1. General Guidelines • • • • • • • •

Provide a good power source, minimizing noise from switching power supply circuits (<100mV).

Verify the ability of critical components, e.g. clock source and transformer, to meet application requirements.

Use bulk capacitors (4.7µF-10µF) between the power and ground planes.

Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes.

Keep de-coupling capacitors as close as possible to the RTL8212/RTL8212N/RTL8211N (within 200 mil).

The transformer should be placed as close as possible to the RTL8212/RTL8212N/RTL8211N (within 12cm).

The RJ-45 phone jack should be placed as close as possible to the transformer. Prevent right angles on all traces.

10.2. MII/GMII/RGMII Signal Layout Guidelines • • •

Keep inter-trace spacing with 3 times of trace width, to reduce crosstalk (for example, if the width of the signal trace is 6 mil, the inter-trace spacing should be 18 mil or more).

For traces longer than 5 inches, guard traces should be placed between signal traces. The guard traces should have many vias to GND.

Place source termination resisters near output pins.

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RTL8212/RTL8212N/RTL8211N Datasheet 10.3. RSGMII Signal Layout Guidelines •

Ensure the differential pairs maintain 100 ohm impedance

• (5/7/5 for 4 Layer PCB: Trace width 5 mil, inter-pair spacing 7 mil, dielectric layer

thickness 4.4 mil) • • • • • •

(9/6/9 for 2 Layer PCB: Trace width 9 mil, inter-pair spacing 6 mil, dielectric layer thickness 59 mil)

Separate the differential pair and other signals by at least 30mil. Keep intra-pair length mismatch less than 5mil.

Place AC coupling capacitors near output pins of differential pairs. Route both traces of differential pairs symmetrically. Avoid vias on differential pairs.

10.4. Ethernet MDI Differential Signal Layout Guidelines • • • •

Ensure the differential pairs maintain 100 ohm impedance and route both traces as identically as possible.

Keep intra-pair length mismatch less than 50mil (from the IC to the transformer and from the transformer to the RJ-45).

Avoid vias on differential pairs.

Maintain a 30mil minimum gap between differential pairs.

10.5. Clock Circuit • •

The clock should be 25M +/-50ppm with jitter less than 0.5ns.

If possible, surround the clock by ground trace to minimize high-frequency emissions.

10.6. Power Planes • •

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

Divide the power plane into 1.2V digital, 1.2V analog, 1.8V analog and 3.3V analog.

Use 0.1µF decoupling capacitors and bulk capacitors between each power plane and ground plane.

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RTL8212/RTL8212N/RTL8211N Datasheet 10.7. Ground Plane • • • •

Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board.

Isolate the AVSS pin of the RTL8212/RTL8212N/RTL8211N (Pin 46, 48 on the QFN76, and Pin 84, 86 on the QFP128) with system ground via beads.

Place a moat (gap) between the system ground and chassis ground.

Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.

10.8. Transformer Options The RTL8212/RTL8212N/RTL8211N uses a transformer with a 1:1 turn ratio. There are many venders offering transformer designs that meet the RTL8212/RTL8212N/RTL8211N’s requirements, e.g., Pulse H5014, Bothhand GS5014R, and LANKom LG-4803-1(R) for the RTL8212/RTL8212N. Pulse H5004 and Bothhand 24HST1041-2 for the RTL8211N.

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RTL8212/RTL8212N/RTL8211N Datasheet 11. Mechanical Dimensions

11.1. EDHS-QFP-128 Dimensions (RTL8212)

See the Mechanical Dimensions notes on the next page.

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RTL8212/RTL8212N/RTL8211N Datasheet 11.2. Notes for EDHS-QFP-128 Dimensions (RTL8212)

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RTL8212/RTL8212N/RTL8211N Datasheet 11.3. QFN-76 Dimensions (RTL8211N & RTL8212N)

See the Mechanical Dimensions notes on the next page.

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver Track ID: JATR-1076-21 Rev. 1.2

RTL8212/RTL8212N/RTL8211N Datasheet 11.4. Notes for QFN-76 Dimensions (RTL8211N & RTL8212N)

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RTL8212/RTL8212N/RTL8211N Datasheet 12. Ordering Information

Table 45. Ordering Information

Part Number Package

RTL8212-GR EDHS QFP-128 in ‘Green’ package RTL8212N-GR QFN-76 in ‘Green’ package RTL8211N-GR QFN-76 in ‘Green’ package Note: See page 14, 15, and 16 for package identification information.

Status

Realtek Semiconductor Corp. Headquarters

No. 2, Innovation Road II

Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw

Integrated 10/100/1000 Single/Dual Gigabit Ethernet Transceiver

66 Track ID: JATR-1076-21 Rev. 1.2