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专利名称：Logical verification apparatus and method
for memory control circuit
发明人：Hiroshi Hosokawa申请号：US10124365申请日：20020418
公开号：US20020157047A1公开日：20021024
专利附图：
摘要：A CPU model issues a memory access request to a memory control circuit byexecuting a verification test program. A transaction monitor monitors a transactiongenerated on a system bus, and detects and holds a transaction of memory access from
the CPU model. A memory model responds to access from the memory control circuit,and acquires transaction information of that access. A memory access checker logicallyverifies the memory control circuit using the transaction information acquired by thememory model, and the transaction information held by the transaction monitor.
申请人：HOSOKAWA HIROSHI
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