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专利名称：SELF-ALIGNED DRAIN/CHANNEL JUNCTION
IN VERTICAL PASS TRANSISTOR DRAM CELLDESIGN FOR DEVICE SCALING
发明人：Geng Wang,Kevin McStay,Mary Elizabeth
Weybright,Yujun Li,Dureseti Chidambarrao
申请号：US10604731申请日：20030813
公开号：US20050037561A1公开日：20050217
专利附图：
摘要：A method of formation of a deep trench vertical transistor is provided. A deep
trench with a sidewall in a doped semiconductor substrate is formed. The semiconductorsubstrate includes a counterdoped drain region in the surface thereof and a channelalongside the sidewall. The drain region has a top level and a bottom level. Acounterdoped source region is formed in the substrate juxtaposed with the sidewallbelow the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposedwith a gate conductor. Perform the step of recessing the gate conductor below thebottom level of the drain region followed by performing angled ion implantation at anangle θ+δ with respect to vertical of a counterdopant into the channel below the sourceregion and performing angled ion implantation at an angle θ with respect to vertical of adopant into the channel below the source region
申请人：Geng Wang,Kevin McStay,Mary Elizabeth Weybright,Yujun Li,DuresetiChidambarrao
地址：Beacon NY 12508 US,Hopewell Junction NY 12533 US,Pleasant Valley NY 12569US,Poughkeepsie NY 12603 US,Weston CT 06883 US
国籍：US,US,US,US,US
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