专利内容由知识产权出版社提供
专利名称：ERROR GENERATING CIRCUIT发明人：ONO SUSUMU,HIROSE KUNIHARU申请号：JP8104785申请日：19850416公开号：JPS61239738A公开日：19861025
摘要：PURPOSE:To adds a random error which has an optional error rate to an inputdigital signal by providing an error generating circuit with a combinational logic circuit andvarying the mark rate of a random pattern with a constant mark rate to an optical markrate and supplying it to an error inserting circuit. CONSTITUTION:When the input digitalsignal VI is caused to have a random error which has an error rate close to, for example,1/10<3>, PN pattern generators 31 and 41 generate an n1-phase and an n2-phase PNpattern signal sequence which are inputted to AND gates 32 and 42 respectively. Thelogical gates 32 and 42 generate random patterns with a 1/2<10> and a 1/2<15> markrate, which are inputted to the combinational logic circuit 50. The combinational logiccircuit 50 ORs the two input random patterns as shown by equation I and generates andsupplies a random pattern with a mark rate A to the error inserting circuit 106. The errorinserting circuit 20 inserts a random error with an (1/2<10>+1/2<15>) into the inputdigital signal VI and sends out an output digital signal VO from an output terminal 13.Consequently, an error rate close to a desired error rate 1/10<3> is obtained.
申请人：OKI ELECTRIC IND CO LTD
更多信息请下载全文后查看
