ADC0804最全英文资料

ADC0801/ADC0802/ADC0803/ADC0804/ADC08058-BitµPCompatibleA/DConverters

GeneralDescription

TheADC0801,ADC0802,ADC0803,ADC0804andADC0805areCMOS8-bitsuccessiveapproximationA/Dconvertersthatuseadifferentialpotentiometricladder—similartothe256Rproducts.TheseconvertersaredesignedtoallowoperationwiththeNSC800andINS8080AderivativecontrolbuswithTRI-STATEoutputlatchesdirectlydrivingthedatabus.TheseA/Dsappearlikememoryloca-tionsorI/Oportstothemicroprocessorandnointerfacinglogicisneeded.

Differentialanalogvoltageinputsallowincreasingthecommon-moderejectionandoffsettingtheanalogzeroinputvoltagevalue.Inaddition,thevoltagereferenceinputcanbeadjustedtoallowencodinganysmalleranalogvoltagespantothefull8bitsofresolution.

nDifferentialanalogvoltageinputs

nLogicinputsandoutputsmeetbothMOSandTTLvoltagelevelspecifications

nWorkswith2.5V(LM336)voltagereferencenOn-chipclockgenerator

n0Vto5Vanaloginputvoltagerangewithsingle5Vsupply

nNozeroadjustrequired

n0.3\"standardwidth20-pinDIPpackage

n20-pinmoldedchipcarrierorsmalloutlinepackagenOperatesratiometricallyorwith5VDC,2.5VDC,oranalogspanadjustedvoltagereference

KeySpecifications

nResolutionnTotalerror

nConversiontime

8bits

±1⁄4LSB,±1⁄2LSBand±1LSB

100µs

Features

nCompatiblewith8080µPderivatives—nointerfacinglogicneeded-accesstime-135ns

nEasyinterfacetoallmicroprocessors,oroperates“standalone”

ConnectionDiagram

ADC080X

Dual-In-LineandSmallOutline(SO)Packages

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SeeOrderingInformation

OrderingInformation

TEMPRANGE

ERROR

0˚CTO70˚CADC0802LCWMADC0804LCWMM20B—Small

Outline

ADC0804LCN0˚CTO70˚C

−40˚CTO+85˚CADC0801LCNADC0802LCNADC0803LCN

ADC0805LCN/ADC0804LCJ

N20A—MoldedDIP

±1⁄4BitAdjusted±1⁄2BitUnadjusted±1⁄2BitAdjusted±1BitUnadjusted

PACKAGEOUTLINE

Z-80®isaregisteredtrademarkofZilogCorp.

©2001NationalSemiconductorCorporationDS005671www.national.com

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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8080Interface

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ErrorSpecification(IncludesFull-Scale,

ZeroError,andNon-Linearity)

PartNumberADC0801ADC0802ADC0803ADC0804ADC0805

Full-ScaleAdjusted

VREF/2=2.500VDC(NoAdjustments)

VREF/2=NoConnection(NoAdjustments)

±1⁄4LSB

±1⁄2LSB

±1⁄2LSB

±1LSB

±1LSB

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805AbsoluteMaximumRatings(Notes1,2)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltage(VCC)(Note3)Voltage

LogicControlInputs

AtOtherInputandOutputs

LeadTemp.(Soldering,10seconds)Dual-In-LinePackage(plastic)Dual-In-LinePackage(ceramic)SurfaceMountPackage

VaporPhase(60seconds)

6.5V

−0.3Vto+18V−0.3Vto(VCC+0.3V)

260˚C300˚C215˚C

Infrared(15seconds)StorageTemperatureRangePackageDissipationatTA=25˚CESDSusceptibility(Note10)220˚C

−65˚Cto+150˚C

875mW800V

OperatingRatings(Notes1,2)

TemperatureRangeADC0804LCJ

ADC0801/02/03/05LCNADC0804LCN

ADC0802/04LCWMRangeofVCCTMIN≤TA≤TMAX−40˚C≤TA≤+85˚C−40˚C≤TA≤+85˚C0˚C≤TA≤+70˚C0˚C≤TA≤+70˚C4.5VDCto6.3VDCElectricalCharacteristics

ThefollowingspecificationsapplyforVCC=5VDC,TMIN≤TA≤TMAXandfCLK=0kHzunlessotherwisespecified.

Parameter

ADC0801:TotalAdjustedError(Note8)ADC0802:TotalUnadjustedError(Note8)ADC0803:TotalAdjustedError(Note8)ADC0804:TotalUnadjustedError(Note8)ADC0805:TotalUnadjustedError(Note8)VREF/2InputResistance(Pin9)AnalogInputVoltageRangeDCCommon-ModeErrorPowerSupplySensitivity

Conditions

WithFull-ScaleAdj.(SeeSection2.5.2)VREF/2=2.500VDCWithFull-ScaleAdj.(SeeSection2.5.2)VREF/2=2.500VDCVREF/2-NoConnectionADC0801/02/03/05ADC0804(Note9)(Note4)V(+)orV(−)OverAnalogInputVoltageRange

VCC=5VDC±10%OverAllowedVIN(+)andVIN(−)VoltageRange(Note4)

2.50.75Gnd–0.05

8.01.1

VCC+0.05

Min

Typ

Max

UnitsLSBLSBLSBLSBLSBkΩkΩVDCLSBLSB

±1⁄4±1⁄2±1⁄2±1±1

±1/16±1/16

±1⁄8±1⁄8ACElectricalCharacteristics

ThefollowingspecificationsapplyforVCC=5VDCandTMIN≤TA≤TMAXunlessotherwisespecified.SymbolTCTCfCLKCRtW(WR)LtACCt1H,t0HParameter

ConversionTimeConversionTimeClockFrequencyClockDutyCycle

ConversionRateinFree-RunningMode

WidthofWRInput(StartPulseWidth)AccessTime(DelayfromFallingEdgeofRDtoOutputDataValid)TRI-STATEControl(DelayfromRisingEdgeofRDtoHi-ZState)

tWI,tRICINDelayfromFallingEdgeofWRorRDtoResetofINTRInputCapacitanceofLogicControlInputs

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Conditions

fCLK=0kHz(Note6)(Notes5,6)VCC=5V,(Note5)INTRtiedtoWRwithCS=0VDC,fCLK=0kHzCS=0VDC(Note7)CL=100pFCL=10pF,RL=10k(SeeTRI-STATETestCircuits)

Min10366100408770100

TypMax11473

Unitsµs1/fCLKkHz%conv/sns

01460609708

135125

200200

nsns

3005

4507.5

nspF

ACElectricalCharacteristics

SymbolCOUTParameter

TRI-STATEOutputCapacitance(DataBuffers)

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ThefollowingspecificationsapplyforVCC=5VDCandTMIN≤TA≤TMAXunlessotherwisespecified.

Conditions

Min

Typ5

Max7.5

UnitspF

CONTROLINPUTS[Note:CLKIN(Pin4)istheinputofaSchmitttriggercircuitandisthereforespecifiedseparately]VIN(1)VIN(0)IIN(1)IIN(0)

Logical“1”InputVoltage(ExceptPin4CLKIN)Logical“0”InputVoltage(ExceptPin4CLKIN)Logical“1”InputCurrent(AllInputs)

Logical“0”InputCurrent(AllInputs)

CLOCKINANDCLOCKRVT+VT−VHVOUT(0)VOUT(1)

CLKIN(Pin4)PositiveGoingThresholdVoltageCLKIN(Pin4)NegativeGoingThresholdVoltageCLKIN(Pin4)Hysteresis(VT+)−(VT−)

Logical“0”CLKROutputVoltage

Logical“1”CLKROutputVoltage

DATAOUTPUTSANDINTRVOUT(0)

Logical“0”OutputVoltageDataOutputsINTROutput

VOUT(1)VOUT(1)IOUTISOURCEISINKPOWERSUPPLYICCSupplyCurrent(IncludesLadderCurrent)

ADC0801/02/03/04LCJ/05ADC0804LCN/LCWM

fCLK=0kHz,VREF/2=NC,TA=25˚CandCS=5V

1.11.9

1.82.5

mAmA

Logical“1”OutputVoltageLogical“1”OutputVoltageTRI-STATEDisabledOutputLeakage(AllDataBuffers)

IOUT=1.6mA,VCC=4.75VDCIOUT=1.0mA,VCC=4.75VDCIO=−360µA,VCC=4.75VDCIO=−10µA,VCC=4.75VDCVOUT=0VDCVOUT=5VDCVOUTShorttoGnd,TA=25˚CVOUTShorttoVCC,TA=25˚C

4.59.0

616

2.44.5−3

30.40.4

VDCVDCVDCVDCµADCµADCmADCmADCIO=360µAVCC=4.75VDCIO=−360µAVCC=4.75VDC2.4

VDC0.4

VDC0.6

1.3

2.0

VDC1.5

1.8

2.1

VDC2.7

3.1

3.5

VDCVIN=0VDC−1

−0.005

µADCVIN=5VDC0.005

1

µADCVCC=4.75VDC0.8

VDCVCC=5.25VDC2.0

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VDCNote1:AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.DCandACelectricalspecificationsdonotapplywhenoperatingthedevicebeyonditsspecifiedoperatingconditions.

Note2:AllvoltagesaremeasuredwithrespecttoGnd,unlessotherwisespecified.TheseparateAGndpointshouldalwaysbewiredtotheDGnd.Note3:Azenerdiodeexists,internally,fromVCC

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805ACElectricalCharacteristics

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Note7:TheCSinputisassumedtobrackettheWRstrobeinputandthereforetimingisdependentontheWRpulsewidth.AnarbitrarilywidepulsewidthwillholdtheconverterinaresetmodeandthestartofconversionisinitiatedbythelowtohightransitionoftheWRpulse(seetimingdiagrams).

Note8:NoneoftheseA/Dsrequiresazeroadjust(seesection2.5.1).Toobtainzerocodeatotheranaloginputvoltagesseesection2.5andFigure7.Note9:TheVREF/2pinisthecenterpointofatwo-resistordividerconnectedfromVCCtoground.InallversionsoftheADC0801,ADC0802,ADC0803,andADC0805,andintheADC0804LCJ,eachresistoristypically16kΩ.InallversionsoftheADC0804excepttheADC0804LCJ,eachresistoristypically2.2kΩ.Note10:Humanbodymodel,100pFdischargedthrougha1.5kΩresistor.

TypicalPerformanceCharacteristics

LogicInputThresholdVoltagevs.SupplyVoltage

DelayFromFallingEdgeofRDtoOutputDataValidvs.LoadCapacitance

CLKINSchmittTripLevelsvs.SupplyVoltage

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fCLKvs.ClockCapacitor

Full-ScaleErrorvsConversionTime

EffectofUnadjustedOffsetErrorvs.VREF/2Voltage

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OutputCurrentvsTemperature

PowerSupplyCurrentvsTemperature(Note9)

LinearityErroratLowVREF/2Voltages

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TRI-STATETestCircuitsandWaveforms

t1Ht1H,CL=10pF

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tr=20ns

t0Ht0H,CL=10pF

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tr=20ns

TimingDiagrams

(Alltimingismeasuredfromthe50%voltagepoints)

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TimingDiagrams

(Alltimingismeasuredfromthe50%voltagepoints)(Continued)

OutputEnableandResetwithINTR

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Note:Readstrobemustoccur8clockperiods(8/fCLK)afterassertionofinterrupttoguaranteeresetofINTR.

TypicalApplications

6800Interface

RatiometericwithFull-ScaleAdjust

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Note:beforeusingcapsatVINorVREF/2,seesection2.3.2InputBypassCapacitors.

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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Absolutewitha5VReference

Absolutewitha2.500VReference

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*Forlowpower,seealsoLM385–2.5

Zero-ShiftandSpanAdjust:2V≤VIN≤5VSpanAdjust:0V≤VIN≤3V

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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AµPInterfacedComparator

DirectlyConvertingaLow-LevelSignal

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For:

VIN(+)>VIN(−)Output=FFHEXFor:

VIN(+)VREF/2=256mV

1mVResolutionwithµPControlledRange

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VREF/2=128mV1LSB=1mV

VDAC≤VIN≤(VDAC+256mV)0≤VDAC<2.5V

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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DigitizingaCurrentFlow

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Self-ClockingMultipleA/DsExternalClocking

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100kHz≤fCLK≤1460kHz

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*UsealargeRvaluetoreduceloadingatCLKRoutput.

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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Self-ClockinginFree-RunningMode

µPInterfaceforFree-RunningA/D

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*Afterpower-up,amomentarygroundingoftheWRinputisneededtoguaranteeoperation.

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Operatingwith“Automotive”RatiometricTransducers

RatiometricwithVREF/2Forced

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*VIN(−)=0.15VCC

15%ofVCC≤VXDR≤85%ofVCC

µPCompatibleDifferential-InputComparatorwithPre-SetVOS(withorwithoutHysteresis)

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*SeeFigure5toselectRvalue

DB7=“1”forVIN(+)>VIN(−)+(VREF/2)Omitcircuitrywithinthedottedareaifhysteresisisnotneeded

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TypicalApplications

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Low-Cost,µPInterfaced,Temperature-to-Digital

Converter

Handling±10VAnalogInputs

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*BeckmanInstruments#694-3-R10Kresistorarray

µPInterfacedTemperature-to-DigitalConverter

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*Circuitvaluesshownarefor0˚C≤TA≤+128˚C***

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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Read-OnlyInterface

Handling±5VAnalogInputs

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*BeckmanInstruments#694-3-R10Kresistorarray

µPInterfacedComparatorwithHysteresisProtectingtheInput

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Diodesare1N914

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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AnalogSelf-TestforaSystem

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*LM3transistors

A,B,C,D=LM324Aquadopamp

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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3-DecadeLogarithmicA/DConverter

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NoiseFilteringtheAnalogInputMultiplexingDifferentialInputs

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fC=20Hz

UsesChebyshevimplementationforsteeperroll-offunity-gain,2ndorder,low-passfilter

Addingaseparatefilterforeachchannelincreasessystemresponsetimeifananalogmultiplexerisused

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OutputBufferswithA/DDataEnabledIncreasingBusDriveand/orReducingTimeonBus

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*A/Doutputdataisupdated1CLKperiodpriortoassertionofINTR

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805TypicalApplications

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SamplinganACInputSignal

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Note11:Oversamplewheneverpossible[keepfs

>2f(−60)]toeliminateinputfrequencyfolding(aliasing)andtoallowfortheskirtresponseofthefilter.

Note12:Considertheamplitudeerrorswhichareintroducedwithinthepassbandofthefilter.

70%PowerSavingsbyClockGating

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(Completeshutdowntakes≈30seconds.)

PowerSavingsbyA/DandVREFShutdown

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*UseADC0801,02,03or05forlowestpowerconsumption.

Note:LogicinputscanbedriventoVCCwithA/Dsupplyatzerovolts.

BufferpreventsdatabusfromoverdrivingoutputofA/Dwheninshutdownmode.

FunctionalDescription

1.0UNDERSTANDINGA/DERRORSPECS

AperfectA/Dtransfercharacteristic(staircasewaveform)isshowninFigure1.Thehorizontalscaleisanaloginputvoltageandtheparticularpointslabeledareinstepsof1LSB(19.53mVwith2.5VtiedtotheVREF/2pin).Thedigitaloutputcodesthatcorrespondtotheseinputsareshownas

D−1,D,andD+1.FortheperfectA/D,notonlywillcenter-value(A−1,A,A+1,....)analoginputsproducethecorrectoutputdigitalcodes,butalsoeachriser(thetransitionsbetweenadjacentoutputcodes)willbelocated±1⁄2LSBawayfromeachcenter-value.Asshown,therisersareidealandhavenowidth.Correctdigitaloutputcodeswillbeprovidedforarangeofanaloginputvoltagesthatextend

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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±1⁄2LSBfromtheidealcenter-values.Eachtread(therange

ofanaloginputvoltagethatprovidesthesamedigitaloutputcode)istherefore1LSBwide.

Figure2showsaworstcaseerrorplotfortheADC0801.Allcenter-valuedinputsareguaranteedtoproducethecorrectoutputcodesandtheadjacentrisersareguaranteedtobenoclosertothecenter-valuepointsthan±1⁄4LSB.Inotherwords,ifweapplyananaloginputequaltothecenter-value±1⁄4LSB,weguaranteethattheA/Dwillproducethecorrectdigitalcode.Themaximumrangeofthepositionofthecodetransitionisindicatedbythehorizontalarrowanditisguar-anteedtobenomorethan1⁄2LSB.

TheerrorcurveofFigure3showsaworstcaseerrorplotfortheADC0802.HereweguaranteethatifweapplyananaloginputequaltotheLSBanalogvoltagecenter-valuetheA/Dwillproducethecorrectdigitalcode.

TransferFunction

Nexttoeachtransferfunctionisshownthecorrespondingerrorplot.Manypeoplemaybemorefamiliarwitherrorplotsthantransferfunctions.TheanaloginputvoltagetotheA/DisprovidedbyeitheralinearramporbythediscreteoutputstepsofahighresolutionDAC.Noticethattheerroriscontinuouslydisplayedandincludesthequantizationuncer-taintyoftheA/D.Forexampletheerroratpoint1ofFigure1is+1⁄2LSBbecausethedigitalcodeappeared1⁄2LSBinadvanceofthecenter-valueofthetread.Theerrorplotsalwayshaveaconstantnegativeslopeandtheabruptup-sidestepsarealways1LSBinmagnitude.

ErrorPlot

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FIGURE1.ClarifyingtheErrorSpecsofanA/DConverter

Accuracy=±0LSB:APerfectA/D

TransferFunction

ErrorPlot

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FIGURE2.ClarifyingtheErrorSpecsofanA/DConverter

Accuracy=±1⁄4LSB

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

TransferFunction

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ErrorPlot

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FIGURE3.ClarifyingtheErrorSpecsofanA/DConverter

Accuracy=±1⁄2LSB

2.0FUNCTIONALDESCRIPTION

TheADC0801seriescontainsacircuitequivalentofthe256Rnetwork.Analogswitchesaresequencedbysucces-siveapproximationlogictomatchtheanalogdifferenceinputvoltage[VIN(+)−VIN(−)]toacorrespondingtapontheRnetwork.Themostsignificantbitistestedfirstandafter8comparisons(clockcycles)adigital8-bitbinarycode(11111111=full-scale)istransferredtoanoutputlatchandthenaninterruptisasserted(INTRmakesahigh-to-lowtransition).Aconversioninprocesscanbeinterruptedbyissuingasecondstartcommand.Thedevicemaybeoper-atedinthefree-runningmodebyconnectingINTRtotheWRinputwithCS=0.Toensurestart-upunderallpossibleconditions,anexternalWRpulseisrequiredduringthefirstpower-upcycle.

Onthehigh-to-lowtransitionoftheWRinputtheinternalSARlatchesandtheshiftregisterstagesarereset.AslongastheCSinputandWRinputremainlow,theA/Dwillremaininaresetstate.Conversionwillstartfrom1to8clockperiodsafteratleastoneoftheseinputsmakesalow-to-hightransition.

AfunctionaldiagramoftheA/DconverterisshowninFigure4.Allofthepackagepinoutsareshownandthemajorlogiccontrolpathsaredrawninheavierweightlines.

TheconverterisstartedbyhavingCSandWRsimulta-neouslylow.Thissetsthestartflip-flop(F/F)andtheresult-ing“1”levelresetsthe8-bitshiftregister,resetstheInterrupt(INTR)F/Fandinputsa“1”totheDflop,F/F1,whichisattheinputendofthe8-bitshiftregister.Internalclocksignalsthentransferthis“1”totheQoutputofF/F1.TheANDgate,G1,combinesthis“1”outputwithaclocksignaltoprovidearesetsignaltothestartF/F.Ifthesetsignalisnolongerpresent(eitherWRorCSisa“1”)thestartF/Fisresetandthe8-bitshiftregisterthencanhavethe“1”clockedin,whichstartstheconversionprocess.Ifthesetsignalweretostillbepresent,thisresetpulsewouldhavenoeffect(bothoutputsofthestartF/Fwouldmomentarilybeata“1”level)andthe8-bitshiftregisterwouldcontinuetobeheldintheresetmode.ThislogicthereforeallowsforwideCSandWRsignalsandtheconverterwillstartafteratleastoneofthesesignalsreturnshighandtheinternalclocksagainprovidearesetsignalforthestartF/F.

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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Note13:CSshowntwiceforclarity.

Note14:SAR=SuccessiveApproximationRegister.

FIGURE4.BlockDiagram

Afterthe“1”isclockedthroughthe8-bitshiftregister(whichcompletestheSARsearch)itappearsastheinputtotheD-typelatch,LATCH1.Assoonasthis“1”isoutputfromtheshiftregister,theANDgate,G2,causesthenewdigitalwordtotransfertotheTRI-STATEoutputlatches.WhenLATCH1issubsequentlyenabled,theQoutputmakesahigh-to-lowtransitionwhichcausestheINTRF/Ftoset.AninvertingbufferthensuppliestheINTRinputsignal.

NotethatthisSETcontroloftheINTRF/Fremainslowfor8oftheexternalclockperiods(astheinternalclocksrunat1⁄8ofthefrequencyoftheexternalclock).Ifthedataoutputiscontinuouslyenabled(CSandRDbothheldlow),theINTRoutputwillstillsignaltheendofconversion(byahigh-to-lowtransition),becausetheSETinputcancontroltheQoutputoftheINTRF/FeventhoughtheRESETinputisconstantlyata“1”levelinthisoperatingmode.ThisINTRoutputwillthereforestaylowforthedurationoftheSETsignal,whichis8periodsoftheexternalclockfrequency(assumingtheA/Disnotstartedduringthisinterval).

Whenoperatinginthefree-runningorcontinuousconversionmode(INTRpintiedtoWRandCSwiredlow—seealsosection2.8),theSTARTF/FisSETbythehigh-to-lowtran-sitionoftheINTRsignal.ThisresetstheSHIFTREGISTER

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whichcausestheinputtotheD-typelatch,LATCH1,togolow.Asthelatchenableinputisstillpresent,theQoutputwillgohigh,whichthenallowstheINTRF/FtobeRESET.ThisreducesthewidthoftheresultingINTRoutputpulsetoonlyafewpropagationdelays(approximately300ns).

Whendataistoberead,thecombinationofbothCSandRDbeinglowwillcausetheINTRF/FtoberesetandtheTRI-STATEoutputlatcheswillbeenabledtoprovidethe8-bitdigitaloutputs.

2.1DigitalControlInputs

Thedigitalcontrolinputs(CS,RD,andWR)meetstandardT2Llogicvoltagelevels.ThesesignalshavebeenrenamedwhencomparedtothestandardA/DStartandOutputEnablelabels.Inaddition,theseinputsareactivelowtoallowaneasyinterfacetomicroprocessorcontrolbusses.Fornon-microprocessorbasedapplications,theCSinput(pin1)canbegroundedandthestandardA/DStartfunctionisobtainedbyanactivelowpulseappliedattheWRinput(pin3)andtheOutputEnablefunctioniscausedbyanactivelowpulseattheRDinput(pin2).

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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2.2AnalogDifferentialVoltageInputsandCommon-ModeRejection

ThisA/Dhasadditionalapplicationsflexibilityduetotheanalogdifferentialvoltageinput.TheVIN(−)input(pin7)canbeusedtoautomaticallysubtractafixedvoltagevaluefromtheinputreading(tarecorrection).Thisisalsousefulin4mA–20mAcurrentloopconversion.Inaddition,common-modenoisecanbereducedbyuseofthedifferen-tialinput.

ThetimeintervalbetweensamplingVIN(+)andVIN(−)is4-1⁄2clockperiods.Themaximumerrorvoltageduetothisslighttimedifferencebetweentheinputvoltagesamplesisgivenby:

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rONofSW1andSW2.5kΩ

r=rONCSTRAY.5kΩx12pF=60ns

FIGURE5.AnalogInputImpedance

where:

∆VeistheerrorvoltageduetosamplingdelayVPisthepeakvalueofthecommon-modevoltagefcmisthecommon-modefrequency

Asanexample,tokeepthiserrorto1⁄4LSB(∼5mV)whenoperatingwitha60Hzcommon-modefrequency,fcm,andusinga0kHzA/Dclock,fCLK,wouldallowapeakvalueofthecommon-modevoltage,VP,whichisgivenby:

ThevoltageonthiscapacitanceisswitchedandwillresultincurrentsenteringtheVIN(+)inputpinandleavingtheVIN(−)inputwhichwilldependontheanalogdifferentialinputvolt-agelevels.Thesecurrenttransientsoccurattheleadingedgeoftheinternalclocks.Theyrapidlydecayanddonotcauseerrorsastheon-chipcomparatorisstrobedattheendoftheclockperiod.

FaultMode

IfthevoltagesourceappliedtotheVIN(+)orVIN(−)pinexceedstheallowedoperatingrangeofVCC+50mV,largeinputcurrentscanflowthroughaparasiticdiodetotheVCCpin.Ifthesecurrentscanexceedthe1mAmaxallowedspec,anexternaldiode(1N914)shouldbeaddedtobypassthiscurrenttotheVCCpin(withthecurrentbypassedwiththisdiode,thevoltageattheVIN(+)pincanexceedtheVCCvoltagebytheforwardvoltageofthisdiode).

2.3.2InputBypassCapacitors

BypasscapacitorsattheinputswillaveragethesechargesandcauseaDCcurrenttoflowthroughtheoutputresis-tancesoftheanalogsignalsources.ThischargepumpingactionisworseforcontinuousconversionswiththeVIN(+)inputvoltageatfull-scale.Forcontinuousconversionswitha0kHzclockfrequencywiththeVIN(+)inputat5V,thisDCcurrentisatamaximumofapproximately5µA.Therefore,bypasscapacitorsshouldnotbeusedattheanaloginputsortheVREF/2pinforhighresistancesources(>1kΩ).Ifinputbypasscapacitorsarenecessaryfornoisefilteringandhighsourceresistanceisdesirabletominimizecapacitorsize,thedetrimentaleffectsofthevoltagedropacrossthisinputresistance,whichisduetotheaveragevalueoftheinputcurrent,canbeeliminatedwithafull-scaleadjustmentwhilethegivensourceresistorandinputbypasscapacitorarebothinplace.Thisispossiblebecausetheaveragevalueoftheinputcurrentisapreciselinearfunctionofthedifferentialinputvoltage.

2.3.3InputSourceResistance

Largevaluesofsourceresistancewhereaninputbypasscapacitorisnotused,willnotcauseerrorsastheinputcurrentssettleoutpriortothecomparisontime.Ifalowpassfilterisrequiredinthesystem,usealowvaluedseriesresistor(≤1kΩ)forapassiveRCsectionoraddanopampRCactivelowpassfilter.Forlowsourceresistanceapplica-tions,(≤1kΩ),a0.1µFbypasscapacitorattheinputswillpreventnoisepickupduetoseriesleadinductanceofalong

or

whichgivesVP.1.9V.

Theallowedrangeofanaloginputvoltagesusuallyplacesmoresevererestrictionsoninputcommon-modenoiselev-els.

Ananaloginputvoltagewithareducedspanandarelativelylargezerooffsetcanbehandledeasilybymakinguseofthedifferentialinput(seesection2.4ReferenceVoltage).2.3AnalogInputs2.31InputCurrent

NormalMode

Duetotheinternalswitchingaction,displacementcurrentswillflowattheanaloginputs.Thisisduetoon-chipstraycapacitancetogroundasshowninFigure5.

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FunctionalDescription

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wire.A100Ωseriesresistorcanbeusedtoisolatethiscapacitor—boththeRandCareplacedoutsidethefeed-backloop—fromtheoutputofanopamp,ifused.2.3.4Noise

Theleadstotheanaloginputs(pins6and7)shouldbekeptasshortaspossibletominimizeinputnoisecoupling.Bothnoiseandundesireddigitalclockcouplingtotheseinputscancausesystemerrors.Thesourceresistancefortheseinputsshould,ingeneral,bekeptbelow5kΩ.Largervaluesofsourceresistancecancauseundesiredsystemnoisepickup.Inputbypasscapacitors,placedfromtheanaloginputstoground,willeliminatesystemnoisepickupbutcancreateanalogscaleerrorsasthesecapacitorswillaveragethetransientinputswitchingcurrentsoftheA/D(seesection2.3.1.).Thisscaleerrordependsonbothalargesourceresistanceandtheuseofaninputbypasscapacitor.Thiserrorcanbeeliminatedbydoingafull-scaleadjustmentoftheA/D(adjustVREF/2foraproperfull-scalereading—seesection2.5.2onFull-ScaleAdjustment)withthesourcere-sistanceandinputbypasscapacitorinplace.2.4ReferenceVoltage

2.4.1SpanAdjust

Formaximumapplicationsflexibility,theseA/Dshavebeendesignedtoaccommodatea5VDC,2.5VDCoranadjustedvoltagereference.ThishasbeenachievedinthedesignoftheICasshowninFigure6.

NoticethatthereferencevoltagefortheICiseither1⁄2ofthevoltageappliedtotheVCCsupplypin,orisequaltothevoltagethatisexternallyforcedattheVREF/2pin.ThisallowsforaratiometricvoltagereferenceusingtheVCCsupply,a5VDCreferencevoltagecanbeusedfortheVCCsupplyoravoltagelessthan2.5VDCcanbeappliedtotheVREF/2inputforincreasedapplicationflexibility.TheinternalgaintotheVREF/2inputis2,makingthefull-scaledifferentialinputvoltagetwicethevoltageatpin9.

Anexampleoftheuseofanadjustedreferencevoltageistoaccommodateareducedspan—ordynamicvoltagerangeoftheanaloginputvoltage.Iftheanaloginputvoltageweretorangefrom0.5VDCto3.5VDC,insteadof0Vto5VDC,thespanwouldbe3VasshowninFigure7.With0.5VDCappliedtotheVIN(−)pintoabsorbtheoffset,thereferencevoltagecanbemadeequalto1⁄2ofthe3Vspanor1.5VDC.TheA/DnowwillencodetheVIN(+)signalfrom0.5Vto3.5Vwiththe0.5Vinputcorrespondingtozeroandthe3.5VDCinputcorrespondingtofull-scale.Thefull8bitsofresolutionarethereforeappliedoverthisreducedanaloginputvoltagerange.

2.4.2ReferenceAccuracyRequirements

Theconvertercanbeoperatedinaratiometricmodeoranabsolutemode.Inratiometricconverterapplications,themagnitudeofthereferencevoltageisafactorinboththeoutputofthesourcetransducerandtheoutputoftheA/Dconverterandthereforecancelsoutinthefinaldigitaloutputcode.TheADC0805isspecifiedparticularlyforuseinratio-metricapplicationswithnoadjustmentsrequired.Inabsoluteconversionapplications,boththeinitialvalueandthetem-peraturestabilityofthereferencevoltageareimportantfac-torsintheaccuracyoftheA/Dconverter.ForV

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a)AnalogInputSignalExample

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*AddifVREF/2≤1VDCwithLM358todraw3mAtoground.

b)AccommodatinganAnalogInputfrom

0.5V(DigitalOut=00HEX)to3.5V

(DigitalOut=FFHEX)

FIGURE7.AdaptingtheA/DAnalogInputVoltagestoMatchanArbitraryInputSignalRange

2.5ErrorsandReferenceVoltageAdjustments

2.5.1ZeroError

ThezerooftheA/Ddoesnotrequireadjustment.Iftheminimumanaloginputvoltagevalue,VIN(MIN),isnotground,azerooffsetcanbedone.Theconvertercanbemadetooutput00000000digitalcodeforthisminimuminputvoltagebybiasingtheA/DVIN(−)inputatthisVIN(MIN)value(seeApplicationssection).Thisutilizesthedifferentialmodeop-erationoftheA/D.

ThezeroerroroftheA/DconverterrelatestothelocationofthefirstriserofthetransferfunctionandcanbemeasuredbygroundingtheVIN(−)inputandapplyingasmallmagnitudepositivevoltagetotheVIN(+)input.Zeroerroristhediffer-encebetweentheactualDCinputvoltagethatisnecessarytojustcauseanoutputdigitalcodetransitionfrom00000000to00000001andtheideal1⁄2LSBvalue(1⁄2LSB=9.8mVforVREF/2=2.500VDC).

2.5.2Full-Scale

Thefull-scaleadjustmentcanbemadebyapplyingadiffer-entialinputvoltagethatis11⁄2LSBlessthanthedesiredanalogfull-scalevoltagerangeandthenadjustingthemag-nitudeoftheVREF/2input(pin9ortheVCCsupplyifpin9isnotused)foradigitaloutputcodethatisjustchangingfrom11111110to11111111.

2.5.3AdjustingforanArbitraryAnalogInputVoltageRange

IftheanalogzerovoltageoftheA/Disshiftedawayfromground(forexample,toaccommodateananaloginputsignalthatdoesnotgotoground)thisnewzeroreferenceshouldbeproperlyadjustedfirst.AVIN(+)voltagethatequalsthisdesiredzeroreferenceplus1⁄2LSB(wheretheLSBiscal-culatedforthedesiredanalogspan,1LSB=analogspan/

256)isappliedtopin6andthezeroreferencevoltageatpin7shouldthenbeadjustedtojustobtainthe00HEXto01HEXcodetransition.

Thefull-scaleadjustmentshouldthenbemade(withtheproperVIN(−)voltageapplied)byforcingavoltagetotheVIN(+)inputwhichisgivenby:

where:

VMAX=Thehighendoftheanaloginputrangeand

VMIN=thelowend(theoffsetzero)oftheanalogrange.(Botharegroundreferenced.)

TheVREF/2(orVCC)voltageisthenadjustedtoprovideacodechangefromFEHEXtoFFHEX.Thiscompletestheadjustmentprocedure.

2.6ClockingOption

TheclockfortheA/DcanbederivedfromtheCPUclockoranexternalRCcanbeaddedtoprovideself-clocking.TheCLKIN(pin4)makesuseofaSchmitttriggerasshowninFigure8.

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(lowpowerSchottkysuchastheDM74LS240seriesisrec-ommended)orspecialhigherdrivecurrentproductswhicharedesignedasbusdrivers.HighcurrentbipolarbusdriverswithPNPinputsarerecommended.

2.10PowerSupplies

NoisespikesontheVCCsupplylinecancauseconversionerrorsasthecomparatorwillrespondtothisnoise.AlowinductancetantalumfiltercapacitorshouldbeusedclosetotheconverterVCCpinandvaluesof1µForgreaterarerecommended.Ifanunregulatedvoltageisavailableinthesystem,aseparateLM340LAZ-5.0,TO-92,5Vvoltageregu-latorfortheconverter(andotheranalogcircuitry)willgreatlyreducedigitalnoiseontheVCCsupply.

2.11WiringandHook-UpPrecautions

StandarddigitalwirewrapsocketsarenotsatisfactoryforbreadboardingthisA/Dconverter.SocketsonPCboardscanbeusedandalllogicsignalwiresandleadsshouldbegroupedandkeptasfarawayaspossiblefromtheanalogsignalleads.Exposedleadstotheanaloginputscancauseundesireddigitalnoiseandhumpickup,thereforeshieldedleadsmaybenecessaryinmanyapplications.

Asinglepointanaloggroundthatisseparatefromthelogicgroundpointsshouldbeused.Thepowersupplybypasscapacitorandtheself-clockingcapacitor(ifused)shouldbothbereturnedtodigitalground.AnyVREF/2bypassca-pacitors,analoginputfiltercapacitors,orinputsignalshield-ingshouldbereturnedtotheanaloggroundpoint.AtestforpropergroundingistomeasurethezeroerroroftheA/Dconverter.Zeroerrorsinexcessof1⁄4LSBcanusuallybetracedtoimproperboardlayoutandwiring(seesection2.5.1formeasuringthezeroerror).

3.0TESTINGTHEA/DCONVERTER

Therearemanydegreesofcomplexityassociatedwithtest-inganA/Dconverter.OneofthesimplesttestsistoapplyaknownanaloginputvoltagetotheconverteranduseLEDstodisplaytheresultingdigitaloutputcodeasshowninFigure9.Foreaseoftesting,theVREF/2(pin9)shouldbesuppliedwith2.560VDCandaVCCsupplyvoltageof5.12VDCshouldbeused.ThisprovidesanLSBvalueof20mV.

Ifafull-scaleadjustmentistobemade,ananaloginputvoltageof5.090VDC(5.120–11⁄2LSB)shouldbeappliedtotheVIN(+)pinwiththeVIN(−)pingrounded.ThevalueoftheVREF/2inputvoltageshouldthenbeadjusteduntilthedigitaloutputcodeisjustchangingfrom11111110to11111111.ThisvalueofVREF/2shouldthenbeusedforallthetests.ThedigitaloutputLEDdisplaycanbedecodedbydividingthe8bitsinto2hexcharacters,the4mostsignificant(MS)andthe4leastsignificant(LS).Table1showsthefractionalbinaryequivalentofthesetwo4-bitgroups.Byaddingthevoltagesobtainedfromthe“VMS”and“VLS”columnsinTable1,thenominalvalueofthedigitaldisplay(whenVREF/2=2.560V)canbedetermined.Forexample,foranoutputLEDdisplayof10110110orB6(inhex),thevoltagevaluesfromthetableare3.520+0.120or3.0VDC.Thesevoltagevaluesrepresentthecenter-valuesofaperfectA/Dconverter.Theeffectsofquantizationerrorhavetobeac-countedforintheinterpretationofthetestresults.

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FIGURE8.Self-ClockingtheA/D

HeavycapacitiveorDCloadingoftheclockRpinshouldbeavoidedasthiswilldisturbnormalconverteroperation.Loadslessthan50pF,suchasdrivingupto7A/DconverterclockinputsfromasingleclockRpinof1converter,areallowed.Forlargerclocklineloading,aCMOSorlowpowerTTLbufferorPNPinputlogicshouldbeusedtominimizetheloadingontheclockRpin(donotuseastandardTTLbuffer).

2.7RestartDuringaConversion

IftheA/Disrestarted(CSandWRgolowandreturnhigh)duringaconversion,theconverterisresetandanewcon-versionisstarted.Theoutputdatalatchisnotupdatediftheconversioninprocessisnotallowedtobecompleted,there-forethedataofthepreviousconversionremainsinthislatch.TheINTRoutputsimplyremainsatthe“1”level.

2.8ContinuousConversions

Foroperationinthefree-runningmodeaninitializingpulseshouldbeused,followingpower-up,toensurecircuitopera-tion.Inthisapplication,theCSinputisgroundedandtheWRinputistiedtotheINTRoutput.ThisWRandINTRnodeshouldbemomentarilyforcedtologiclowfollowingapower-upcycletoguaranteeoperation.

2.9DrivingtheDataBus

ThisMOSA/D,likeMOSmicroprocessorsandmemories,willrequireabusdriverwhenthetotalcapacitanceofthedatabusgetslarge.Othercircuitry,whichistiedtothedatabus,willaddtothetotalcapacitiveloading,eveninTRI-STATE(highimpedancemode).Backplanebussingalsogreatlyaddstothestraycapacitanceofthedatabus.Therearesomealternativesavailabletothedesignertohandlethisproblem.Basically,thecapacitiveloadingofthedatabusslowsdowntheresponsetime,eventhoughDCspecificationsarestillmet.ForsystemsoperatingwitharelativelyslowCPUclockfrequency,moretimeisavailableinwhichtoestablishproperlogiclevelsonthebusandthereforehighercapacitiveloadscanbedriven(seetypicalcharacteristicscurves).

AthigherCPUclockfrequenciestimecanbeextendedforI/Oreads(and/orwrites)byinsertingwaitstates(8080)orusingclockextendingcircuits(6800).

Finally,iftimeisshortandcapacitiveloadingishigh,externalbusdriversmustbeused.ThesecanbeTRI-STATEbuffers

23

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Forahigherspeedtestsystem,ortoobtainplotteddata,adigital-to-analogconverterisneededforthetestset-up.Anaccurate10-bitDACcanserveastheprecisionvoltagesourcefortheA/D.ErrorsoftheA/Dundertestcanbeexpressedaseitheranalogvoltagesordifferencesin2digitalwords.

AbasicA/DtesterthatusesaDACandprovidestheerrorasananalogoutputvoltageisshowninFigure8.The2opampscanbeeliminatedifalabDVMwithanumericalsubtractionfeatureisavailabletoreadthedifferencevolt-age,“A–C”,directly.Theanaloginputvoltagecanbesup-pliedbyalowfrequencyrampgeneratorandanX-Yplottercanbeusedtoprovideanalogerror(Yaxis)versusanaloginput(Xaxis).

Foroperationwithamicroprocessororacomputer-basedtestsystem,itismoreconvenienttopresenttheerrorsdigitally.ThiscanbedonewiththecircuitofFigure11,wheretheoutputcodetransitionscanbedetectedasthe10-bitDACisincremented.Thisprovides1⁄4LSBstepsforthe8-bitA/Dundertest.IftheresultsofthistestareautomaticallyplottedwiththeanaloginputontheXaxisandtheerror(inLSB’s)astheYaxis,ausefultransferfunctionoftheA/Dundertestresults.Foracceptancetesting,theplotisnotnecessaryandthetestingspeedcanbeincreasedbyestab-lishinginternallimitsontheallowederrorforeachcode.4.0MICROPROCESSORINTERFACING

Todicusstheinterfacewith8080Aand6800microproces-sors,acommonsamplesubroutinestructureisused.ThemicroprocessorstartstheA/D,readsandstorestheresultsof16successiveconversions,thenreturnstotheuser’sprogram.The16databytesarestoredin16successivememorylocations.AllDataandAddresseswillbegiveninhexadecimalform.Softwareandhardwaredetailsarepro-videdseparatelyforeachtypeofmicroprocessor.

4.1Interfacing8080MicroprocessorDerivatives(8048,8085)

Thisconverterhasbeendesignedtodirectlyinterfacewithderivativesofthe8080microprocessor.TheA/Dcanbemappedintomemoryspace(usingstandardmemoryad-dressdecodingforCSandtheMEMRandMEMWstrobes)oritcanbecontrolledasanI/OdevicebyusingtheI/ORandI/OWstrobesanddecodingtheaddressbitsA0→A7(oraddressbitsA8→A15astheywillcontainthesame8-bitaddressinformation)toobtaintheCSinput.UsingtheI/Ospaceprovides256additionaladdressesandmayallowasimpler8-bitaddressdecoderbutthedatacanonlybeinputtotheaccumulator.Tomakeuseoftheadditionalmemoryreferenceinstructions,theA/Dshouldbemappedintomemoryspace.AnexampleofanA/DinI/OspaceisshowninFigure12.

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FIGURE9.BasicA/DTester

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FIGURE10.A/DTesterwithAnalogErrorOutput

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FIGURE11.Basic“Digital”A/DTesterTABLE1.DECODINGTHEDIGITALOUTPUTLEDs

OUTPUTVOLTAGE

FRACTIONALBINARYVALUEFOR

HEX

BINARY

MSGROUP

LSGROUP

VMSGROUP(Note15)

15/256

7/128

13/16

3/4

11/16

5/8

9/16

1/2

7/16

3/8

5/16

1/4

3/16

1/8

1/16

1/128

1/256

1/

3/256

3/128

2/256

1/32

7/256

5/128

9/256

3/

11/25613/256

4.8004.4804.1603.8403.5203.2002.8802.5602.2401.9201.6001.2800.9600.00.3200

CENTERVALUES

WITHVREF/2=2.560VDCVLSGROUP(Note15)0.3000.2800.2600.2400.2200.2000.1800.1600.1400.1200.1000.0800.0600.0400.0200

FEDCBA9876543210

1111111100000000

1111000011110000

1100110011001100

1010101010101010

7/8

15/16

Note15:DisplayOutput=VMSGroup+VLSGroup

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Note16:*PinnumbersfortheDP8228systemcontroller,othersareINS8080A.

Note17:Pin23oftheINS8228mustbetiedto+12Vthrougha1kΩresistortogeneratetheRST7instructionwhenaninterruptisacknowledgedasrequiredbytheaccompanyingsampleprogram.

FIGURE12.ADC0801_INS8080ACPUInterface

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SAMPLEPROGRAMFORFigure12ADC0801–INS8080ACPUINTERFACE

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Note18:ThestackpointermustbedimensionedbecauseaRST7instructionpushesthePContothestack.Note19:Alladdressusedwerearbitrarilychosen.

Thestandardcontrolbussignalsofthe8080CS,RDandWR)canbedirectlywiredtothedigitalcontrolinputsoftheA/Dandthebustimingrequirementsaremettoallowbothstartingtheconverterandoutputtingthedataontothedatabus.AbusdrivershouldbeusedforlargermicroprocessorsystemswherethedatabusleavesthePCboardand/ormustdrivecapacitiveloadslargerthan100pF.

4.1.1Sample8080ACPUInterfacingCircuitryandProgram

ThefollowingsampleprogramandassociatedhardwareshowninFigure12maybeusedtoinputdatafromtheconvertertotheINS8080ACPUchipset(comprisedoftheINS8080Amicroprocessor,theINS8228systemcontrollerandtheINS8224clockgenerator).Forsimplicity,theA/DiscontrolledasanI/Odevice,specificallyan8-bitbi-directionalportlocatedatanarbitrarilychosenportaddress,E0.TheTRI-STATEoutputcapabilityoftheA/Deliminatestheneedforaperipheralinterfacedevice,howeveraddressdecodingisstillrequiredtogeneratetheappropriateCSforthecon-verter.

ItisimportanttonotethatinsystemswheretheA/Dcon-verteris1-of-8orlessI/Omappeddevices,noaddressdecodingcircuitryisnecessary.Eachofthe8addressbits(A0toA7)canbedirectlyusedasCSinputs—oneforeachI/Odevice.

4.1.2INS8048Interface

TheINS8048interfacetechniquewiththeADC0801series(seeFigure13)issimplerthanthe8080ACPUinterface.Thereare24I/Olinesandthreetestinputlinesinthe8048.WiththeseextraI/Olinesavailable,oneoftheI/Olines(bit0ofport1)isusedasthechipselectsignaltotheA/D,thuseliminatingtheuseofanexternaladdressdecoder.BuscontrolsignalsRD,WRandINTofthe8048aretieddirectlytotheA/D.The16converteddatawordsarestoredaton-chipRAMlocationsfrom20to2F(Hex).TheRDandWRsignalsaregeneratedbyreadingfromandwritingintoadummyaddress,respectively.Asampleinterfaceprogramisshownbelow.

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FIGURE13.INS8048Interface

SAMPLEPROGRAMFORFigure13INS8048INTERFACE

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4.2InterfacingtheZ-80

TheZ-80controlbusisslightlydifferentfromthatofthe8080.GeneralRDandWRstrobesareprovidedandsepa-ratememoryrequest,MREQ,andI/Orequest,IORQ,sig-nalsareusedwhichhavetobecombinedwiththegeneral-izedstrobestoprovidetheequivalent8080signals.AnadvantageofoperatingtheA/DinI/OspacewiththeZ-80isthattheCPUwillautomaticallyinsertonewaitstate(theRDandWRstrobesareextendedoneclockperiod)toallowmoretimefortheI/Odevicestorespond.LogictomaptheA/DinI/OspaceisshowninFigure14.

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FIGURE14.MappingtheA/DasanI/ODevice

forUsewiththeZ-80CPUAdditionalI/OadvantagesexistassoftwareDMAroutinesareavailableandusecanbemadeoftheoutputdatatransferwhichexistsontheupper8addresslines(A8to

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A15)duringI/Oinputinstructions.Forexample,MUXchan-nelselectionfortheA/Dcanbeaccomplishedwiththisoperatingmode.

4.3Interfacing6800MicroprocessorDerivatives(6502,etc.)

Thecontrolbusforthe6800microprocessorderivativesdoesnotusetheRDandWRstrobesignals.InsteaditemploysasingleR/Wlineandadditionaltiming,ifneeded,canbederivedfomtheφ2clock.AllI/Odevicesarememorymappedinthe6800system,andaspecialsignal,VMA,indicatesthatthecurrentaddressisvalid.Figure15showsaninterfaceschematicwheretheA/Dismemorymappedinthe6800system.Forsimplicity,theCSdecodingisshownusing1⁄2DM8092.Notethatinmany6800systems,analreadydecoded4/5lineisbroughtouttothecommonbusatpin21.ThiscanbetieddirectlytotheCSpinoftheA/D,providedthatnootherdevicesareaddressedatHXADDR:4XXXor5XXX.

Thefollowingsubroutineperformsessentiallythesamefunc-tionasinthecaseofthe8080Ainterfaceanditcanbecalledfromanywhereintheuser’sprogram.

InFigure16theADC0801seriesisinterfacedtotheM6800microprocessorthrough(thearbitrarilychosen)PortBoftheMC6820orMC6821PeripheralInterfaceAdapter,(PIA).HeretheCSpinoftheA/DisgroundedsincethePIAis

alreadymemorymappedintheM6800systemandnoCSdecodingisnecessary.AlsonoticethattheA/Doutputdatalinesareconnectedtothemicroprocessorbusunderpro-gramcontrolthroughthePIAandthereforetheA/DRDpincanbegrounded.

AsampleinterfaceprogramequivalenttothepreviousoneisshownbelowFigure16.ThePIADataandControlRegistersofPortBarelocatedatHEXaddresses8006and8007,respectively.

5.0GENERALAPPLICATIONS

ThefollowingapplicationsshowsomeinterestingusesfortheA/D.Thefactthatoneparticularmicroprocessorisusedisnotmeanttoberestrictive.Eachoftheseapplicationcircuitswouldhaveitscounterpartusinganymicroprocessorthatisdesired.

5.1MultipleADC0801SeriestoMC6800CPUInterfaceTotransferanalogdatafromseveralchannelstoasinglemicroprocessorsystem,amultipleconverterschemepre-sentsseveraladvantagesovertheconventionalmultiplexersingle-converterapproach.WiththeADC0801series,thedifferentialinputsallowindividualspanadjustmentforeachchannel.Furthermore,allanaloginputchannelsaresensedsimultaneously,whichessentiallydividesthemicroproces-sor’stotalsystemservicingtimebythenumberofchannels,sinceallconversionsoccursimultaneously.ThisschemeisshowninFigure17.

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Note20:NumbersinparenthesesrefertoMC6800CPUpinout.

Note21:NumberorlettersinbracketsrefertostandardM6800systemcommonbuscode.

FIGURE15.ADC0801-MC6800CPUInterface

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SAMPLEPROGRAMFORFigure15ADC0801-MC6800CPUINTERFACE

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Note22:Inorderforthemicroprocessortoservicesubroutinesandinterrupts,thestackpointermustbedimensionedintheuser’sprogram.

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FIGURE16.ADC0801–MC6820PIAInterface

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SAMPLEPROGRAMFORFigure16ADC0801–MC6820PIAINTERFACE

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Thefollowingschematicandsamplesubroutine(DATAIN)maybeusedtointerface(upto)8ADC0801’sdirectlytotheMC6800CPU.Thisschemecaneasilybeextendedtoallowtheinterfaceofmoreconverters.Inthisconfigurationtheconvertersare(arbitrarily)locatedatHEXaddress5000intheMC6800memoryspace.Tosavecomponents,theclocksignalisderivedfromjustoneRCpaironthefirstconverter.ThisoutputdrivestheotherA/Ds.

AlltheconvertersarestartedsimultaneouslywithaSTOREinstructionatHEXaddress5000.NotethatanyotherHEXaddressoftheform5XXXwillbedecodedbythecircuit,pullingalltheCSinputslow.Thiscaneasilybeavoidedbyusingamoredefinitiveaddressdecodingscheme.AlltheinterruptsareORedtogethertoinsurethatallA/Dshavecompletedtheirconversionbeforethemicroprocessorisinterrupted.

Thesubroutine,DATAIN,maybecalledfromanywhereintheuser’sprogram.Oncecalled,thisroutineinitializesthe

CPU,startsalltheconverterssimultaneouslyandwaitsfortheinterruptsignal.Uponreceivingtheinterrupt,itreadstheconverters(fromHEXaddresses5000through5007)andstoresthedatasuccessivelyat(arbitrarilychosen)HEXaddresses0200to0207,beforereturningtotheuser’spro-gram.AllCPUregistersthenrecovertheoriginaldatatheyhadbeforeservicingDATAIN.

5.2Auto-ZeroedDifferentialTransducerAmplifierandA/DConverter

ThedifferentialinputsoftheADC0801serieseliminatetheneedtoperformadifferentialtosingleendedconversionforadifferentialtransducer.Thus,oneopampcanbeelimi-natedsincethedifferentialtosingleendedconversionisprovidedbythedifferentialinputoftheADC0801series.Ingeneral,atransducerpreampisrequiredtotakeadvantageofthefullA/Dconverterinputdynamicrange.

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Note23:

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SAMPLEPROGRAMFORFigure17INTERFACINGMULTIPLEA/D’sINANMC6800SYSTEM

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SAMPLEPROGRAMFORFigure17INTERFACINGMULTIPLEA/D’sINANMC6800SYSTEM

DS005671-A4

Note25:Inorderforthemicroprocessortoservicesubroutinesandinterrupts,thestackpointermustbedimensionedintheuser’sprogram.

ForamplificationofDCinputsignals,amajorsystemerroristheinputoffsetvoltageoftheamplifiersusedforthepreamp.Figure18isagainof100differentialpreampwhoseoffsetvoltageerrorswillbecancelledbyazeroingsubroutinewhichisperformedbytheINS8080Amicroprocessorsys-tem.Thetotalallowableinputoffsetvoltageerrorforthispreampisonly50µVfor1⁄4LSBerror.Thiswouldobviouslyrequireverypreciseamplifiers.Theexpressionforthediffer-entialoutputvoltageofthepreampis:

whereIXisthecurrentthroughresistorRX.Alloftheoffseterrortermscanbecancelledbymaking±IXRX=VOS1+VOS3−VOS2.Thisistheprincipleofthisauto-zeroingscheme.

TheINS8080Ausesthe3I/OportsofanINS8255Progra-mablePeripheralInterface(PPI)tocontroltheautozeroingandinputdatafromtheADC0801asshowninFigure19.ThePPIisprogrammedforbasicI/Ooperation(mode0)withPortAbeinganinputportandPortsBandCbeingoutputports.TwobitsofPortCareusedtoalternatelyopenorclosethe2switchesattheinputofthepreamp.SwitchSW1isclosedtoforcethepreamp’sdifferentialinputtobezeroduringthezeroingsubroutineandthenopenedandSW2isthenclosedforconversionoftheactualdifferentialinputsignal.Using2switchesinthismannereliminatesconcernfortheONresistanceoftheswitchesastheymustconductonlytheinputbiascurrentoftheinputamplifiers.

OutputPortBisusedasasuccessiveapproximationregis-terbythe8080andthebinaryscaledresistorsinserieswitheachoutputbitcreateaD/Aconverter.Duringthezeroingsubroutine,thevoltageatVxincreasesordecreasesasrequiredtomakethedifferentialoutputvoltageequaltozero.ThisisaccomplishedbyensuringthatthevoltageattheoutputofA1isapproximately2.5Vsothatalogic“1”(5V)on

33

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

(Continued)

anyoutputofPortBwillsourcecurrentintonodeVXthusraisingthevoltageatVXandmakingtheoutputdifferentialmorenegative.Conversely,alogic“0”(0V)willpullcurrentoutofnodeVXanddecreasethevoltage,causingthediffer-entialoutputtobecomemorepositive.Fortheresistorval-uesshown,VXcanmove±12mVwitharesolutionof50µV,whichwillnulltheoffseterrortermto1⁄4LSBoffull-scalefor

theADC0801.Itisimportantthatthevoltagelevelsthatdrivetheauto-zeroresistorsbeconstant.Also,forsymmetry,alogicswingof0Vto5Visconvenient.Toachievethis,aCMOSbufferisusedforthelogicoutputsignalsofPortBandthisCMOSpackageispoweredwithastable5Vsource.BufferamplifierA1isnecessarysothatitcansourceorsinktheD/Aoutputcurrent.

DS005671-91

Note26:R2=49.5R1

Note27:SwitchesareLMC13334CMOSanalogswitches.

Note28:The9resistorsusedintheauto-zerosectioncanbe±5%tolerance.

FIGURE18.Gainof100DifferentialTransducerPreamp

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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DS005671-92

FIGURE19.MicroprocessorInterfaceCircuitryforDifferentialPreamp

AflowchartforthezeroingsubroutineisshowninFigure20.ItmustbenotedthattheADC0801serieswilloutputanallzerocodewhenitconvertsanegativeinput[VIN(−)≥VIN(+)].Also,alogicinversionexistsasalloftheI/Oportsarebufferedwithinvertinggates.

Basically,ifthedatareadiszero,thedifferentialoutputvoltageisnegative,soabitinPortBisclearedtopullVXmorenegativewhichwillmaketheoutputmorepositiveforthenextconversion.Ifthedatareadisnotzero,theoutputvoltageispositivesoabitinPortBissettomakeVXmorepositiveandtheoutputmorenegative.Thiscontinuesfor8approximationsandthedifferentialoutputeventuallycon-vergestowithin5mVofzero.

TheactualprogramisgiveninFigure21.AlladdressesusedarecompatiblewiththeBLC80/10microcomputersystem.Inparticular:

PortAandtheADC0801areatportaddressE4PortBisatportaddressE5PortCisatportaddressE6

PPIcontrolwordportisatportaddressE7

ProgramCounterautomaticallygoestoADDR:3C3DuponacknowledgementofaninterruptfromtheADC08015.3MultipleA/DConvertersinaZ-80InterruptDrivenMode

IndataacquisitionsystemswheremorethanoneA/Dcon-verter(orotherperipheraldevice)willbeinterruptingpro-gramexecutionofamicroprocessor,thereisobviouslya

needfortheCPUtodeterminewhichdevicerequiresservic-ing.Figure22andtheaccompanyingsoftwareisamethodofdeterminingwhichof7ADC0801convertershascom-pletedaconversion(INTRasserted)andisrequestinganinterrupt.ThiscircuitallowsstartingtheA/Dconvertersinanysequence,butwillinputandstorevaliddatafromtheconverterswithaprioritysequenceofA/D1beingreadfirst,A/D2second,etc.,throughA/D7whichwouldhavethelowestpriorityfordatabeingread.OnlytheconverterswhoseINTisassertedwillberead.

ThekeytodecodingcircuitryistheDM74LS373,8-bitDtypeflip-flop.WhentheZ-80acknowledgestheinterrupt,theprogramisvectoredtoadatainputZ-80subroutine.ThissubroutinewillreadaperipheralstatuswordfromtheDM74LS373whichcontainsthelogicstateoftheINTRoutputsofalltheconverters.Eachconverterwhichinitiatesaninterruptwillplacealogic“0”inauniquebitpositioninthestatuswordandthesubroutinewilldeterminetheidentityoftheconverterandexecuteadataread.Anidentifierword(whichindicateswhichA/Dthedatacamefrom)isstoredinthenextsequentialmemorylocationabovethelocationofthedatasotheprogramcankeeptrackoftheidentityofthedataentered.

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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FIGURE20.FlowChartforAuto-ZeroRoutine

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

(Continued)

DS005671-A5

Note29:Allnumericalvaluesarehexadecimalrepresentations.

FIGURE21.SoftwareforAuto-ZeroedDifferentialA/D

5.3MultipleA/DConvertersinaZ-80InterruptDrivenMode(Continued)

Thefollowingnotesapply:

•

•

ItisassumedthattheCPUautomaticallyperformsaRST7instructionwhenavalidinterruptisacknowledged(CPUisininterruptmode1).Hence,thesubroutinestartingaddressofX0038.

TheaddressbusfromtheZ-80andthedatabustotheZ-80areassumedtobeinvertedbybusdrivers.A/Ddataandidentifyingwordswillbestoredinsequen-tialmemorylocationsstartingatthearbitrarilychosenaddressX3E00.

Thestackpointermustbedimensionedinthemainpro-gramastheRST7instructionautomaticallypushesthePContothestackandthesubroutineusesanadditional6stackaddresses.

TheperipheralsofconcernaremappedintoI/Ospacewiththefollowingportassignments:

•

••

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FunctionalDescription

HEXPORTADDRESS

00010203

(Continued)PERIPHERAL

HEXPORTADDRESS

040506

PERIPHERALA/D4A/D5A/D6

MM74C3748-bitflip-flopA/D1A/D2A/D3

07A/D7

ThisportaddressalsoservesastheA/Didentifyingwordintheprogram.

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805FunctionalDescription

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DS005671-A6

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805PhysicalDimensions

inches(millimeters)unlessotherwisenoted

SOPackage(M)

OrderNumberADC0802LCWMorADC0804LCWM

NSPackageNumberM20B

MoldedDual-In-LinePackage(N)

OrderNumberADC0801LCN,ADC0802LCN,ADC0803LCN,ADC0804LCNorADC0805LCN

NSPackageNumberN20A

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ADC0801/ADC0802/ADC0803/ADC0804/ADC08058-BitµPCompatibleA/DConvertersNotes

LIFESUPPORTPOLICY

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