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K1B2816B7M

Document Title8Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory

AdvanceUtRAM

Revision HistoryRevision No.History0.0

Initial Draft- Design target

Draft DateRemarkNovember 21, 2003Advance

0.1

RevisedNovember 28, 2003Advance- Added Full Page(256 word, Wrap Around) Burst in burst length- Revised STANDBY MODE STATE MACHINES

- Changed tCHZ, tBHZ, tOHZ in ASYNCHRONOUS AC CHARACTERISTICS from max. 25ns to max. 7ns

- Changed tBEADV in SYNCHRONOUS AC CHARACTERISTICS from min. 15ns to min. 7ns

- Changed tDH in SYNCHRONOUS AC CHARACTERISTICS from min. 1ns to min. 0ns

- Changed tBLZ in SYNCHRONOUS AC CHARACTERISTICS from min. 10ns to min. 5ns

- Changed tOH in ASYNCHRONOUS AC CHARACTERISTICS from min. 10ns to min. 3ns

- Changed tCSS(B) in SYNCHRONOUS AC CHARACTERISTICS from min. 7ns to min. 5ns

- Changed tADVS in SYNCHRONOUS AC CHARACTERISTICS from min. 7ns to min. 5ns

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications andproducts. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

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K1B2816B7M

8M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM

FEATURES

• Process Technology: CMOS• Organization: 8M x16 bit

• Power Supply Voltage: 1.7~2.1V• Three State Outputs

• Supports MRS (Mode Register Set)• MRS control - MRS Pin Control

• Supports Power Saving modes - Deep Power Down mode

AdvanceUtRAM

GENERAL DESCRIPTION

The world is moving into the mobile multi-media era and there-fore the mobile handsets need much bigger memory capacity tohandle the multi-media data.

SAMSUNG’s UtRAM products are designed to meet all therequest from the various customers who want to cope with thefast growing mobile market.

UtRAM is the perfect solution for the mobile market with its lowcost, high density and high performance feature.

K1B2816B7M is fabricated by SAMSUNG′s advanced CMOStechnology using one transistor memory cell.

The device supports the traditional SRAM like asynchronousbus operation(asynchronous page read and asynchronouswrite), the NOR flash like synchronous bus operation(synchro-nous burst read and asynchronous write) and the fully synchro-nous bus operation(synchronous burst read and synchronousburst write).

These three bus operation modes are defined through the moderegister setting.

The device also supports the special features for the standbypower saving. Those are the Deep Power Down(DPD) mode,the Partial Array Refresh(PAR) mode and internal TemperatureCompensated Self Refresh(TCSR) mode.

The optimization of output driver strength is possible through themode register setting to adjust for the different data loadings.Through this output impedance matching, the device can mini-mize the noise generated on the data bus during read operation.

Partial Array Refresh mode Internal TCSR

• Supports Output Impedance Matching for system environment power saving and output drive optimization

• Supports Asynchronous 4-Page Read and Asynchronous Write Operation

• Supports Synchronous Burst Read and Asynchronous Write Operation(Address Latch Type and Low ADV Type)

• Supports Synchronous Burst Read and Synchronous Burst Write Operation

• Synchronous Burst(Read/Write) Operation

- Supports 4 word / 8 word / 16 word and Full page(256 word, Wrap Around) burst

- Supports Linear Burst type & Interleave Burst type - Latency support : Latency 4 & 5 @ 66MHz(tCD 10ns) Latency 4 @ 54MHz(tCD 10ns) - Supports Burst Read Suspend in No Clock toggling

- Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability.• Max. Burst Clock Frequency : 66MHz • Package Type : TBD

Table 1. PRODUCT FAMILY

Product Family

Operating Temp.

Vcc Range

ClockFreq.(Max)66MHz

Power DissipationAsync.

SpeedStandbyDeep powerOperating(tAA)(ISB1, Max.)down(ISBD, Max.)(ICC2, Max.)70ns

TBD

PKG TypeTBD

K1B2816B7M-IIndustrial(-40~85°C)1.7~2.1V

Fig.1 PIN DESCRIPTION

Table 2. PIN DESCRIPTION

NameCLKADVMRS

FunctionClock InputAddress Input ValidMode Register setChip SelectOutput Enable InputWrite Enable InputAddress Inputs

Name

Function

I/O0~I/O15Data Inputs/OutputsVCCVssUBLBWAITDNU

Power SupplyGround

Upper Byte(I/O8~15)Lower Byte(I/O0~7)Data AvailabilityDo Not Use

TBD

CSOEWEA0~A22

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

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K1B2816B7M

CONTENTS

Revision History

Features and General Description Power Up Sequence Functional Description Mode Register Setting Operation Mode Register Setting Timing Asynchronous Operation Asynchronous 4 Page Read Operation Asynchronous Write Operation Asynchronous Write Operation in Synchronous Mode Synchronous Burst Operation Synchronous Burst Read Operation Synchronous Burst Write Operation

Synchronous Burst Operation Terminology Clock

Latency Count Burst Length Burst Stop WAIT Control Burst Type

Low Power Features

Deep Power Down(DPD) Mode Internal TCSR

Output Impedance Matching

Partial Array Refresh(PAR) ModeProduct List

Absolute Maximum Ratings

Recommended DC Operating ConditionsCapacitance

DC and Operating CharacteristicsAsynchronous AC CharacteristicsAsynchronous Timing WaveformsSynchronous AC CharacteristicsSynchronous Timing WaveformsTransition Timing WaveformsPackage Dimension

AdvanceUtRAM

Page

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K1B2816B7M

AdvanceUtRAM

PageLIST of TABLES

Table 1. Product Family Table 2. Pin Description

Table 3. Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table Table 4. Synchronous Burst Read & Asynchronous Write Mode Truth Table Table 5. Synchronous Burst Read & Synchronous Burst Write Mode Truth Table Table 6. Mode Register Setting according to Field of Function Table 7. Mode Register Set

Table 8. MRS AC CharacteristicsTable 9. Latency Count Support

Table 10. Number of Clocks for 1st DataTable 11. Burst Sequence

Table 12. PAR Mode Characteristics Table 13. Product List

Table 14. Absolute Maximum Ratings

Table 15. Recommended DC Operating ConditionsTable 16. Capacitance

Table 17. DC and Operating CharacteristicsTable 18. Asynchronous AC Characteristics

Table 19. Asynchronous Read AC Characteristics

Table 20. Asynchronous Page Read AC Characteristics

Table 21. Asynchronous Write AC Characteristics(WE Controlled)

Table 22. Asynchronous Write AC Characteristics(UB & LB Controlled)

Table 23. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled)Table 24. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled)Table 25. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled)

Table 26. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled)

Table 27. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled)Table 28. Synchronous AC CharacteristicsTable 29. Burst Operation AC Characteristics

Table 30. Burst Read AC Characteristics(CS Toggling Consecutive Burst)Table 31. Burst Read AC Characteristics(CS Low Holding Consecutive Burst)Table 32. Burst Read AC Characteristics(Last Data Sustaining)

Table 33. Burst Write AC Characteristics(CS Toggling Consecutive Burst)Table 34. Burst Write AC Characteristics(CS Low Holding Consecutive Burst)Table 35. Burst Read Stop AC CharacteristicsTable 36. Burst Write Stop AC CharacteristicsTable 37. Burst Read Suspend AC Characteristics

Table 38. Burst Read to Asynch. Write(Address Latch Type) AC CharacteristicsTable 39. Burst Read to Asynch. Write(Low ADV Type) AC Characteristics

Table 40. Asynch. Write(Address Latch Type) to Burst Read AC CharacteristicsTable 41. Asynch. Write(Low ADV Type) to Burst Read AC CharacteristicsTable 42. Burst Read to Burst Write AC CharacteristicsTable 43. Burst Write to Burst Read AC Characteristics

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K1B2816B7M

LIST of FIGURES

Figure 1. Pin Description

Figure 2. Functional Block DiagramFigure 3. Power Up Timing

Figure 4. Standby Mode State Machine Figure 5. Mode Register Setting Timing Figure 6. Asynchronous 4-Page Read Figure 7. Asynchronous Write

Figure 8. Synchronous Burst ReadFigure 9. Synchronous Burst WriteFigure 10. Latency Configuration(Read)

Figure 11. WAIT Control and Read/Write Latency ControlFigure 12. DPD Mode Execution and ExitFigure 13. PAR Mode Execution and Exit

Figure 14. AC Output Load Circuit(Asynchronous)

Figure 15. Timing Waveform of Asynchronous Read CycleFigure 16. Timing Waveform of Page Read Cycle

Figure 17. Timing Waveform of Write Cycle(Asynchronous, WE Controlled)

Figure 18. Timing Waveform of Write Cycle(Asynchronous, UB & LB Controlled)Figure 19. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, WE Controlled)Figure 20. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, UB & LB Controlled)Figure 21. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, WE Controlled)Figure 22. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, UB & LB Controlled)Figure 23. Timing Waveform of Multiple Write Cycle(Asynchronous, Low ADV Type, WE Controlled )Figure 24. AC Output Load Circuit(Synchronous)

Figure 25. Timing Waveform of Basic Burst Operation

Figure 26. Timing Waveform of Burst Read Cycle(CS Toggling Consecutive Burst Read)Figure 27. Timing Waveform of Burst Read Cycle(CS Low Holding Consecutive Burst Read)Figure 28. Timing Waveform of Burst Read Cycle(Last Data Sustaining)

Figure 29. Timing Waveform of Burst Write Cycle(CS Toggling Consecutive Burst Write)Figure 30. Timing Waveform of Burst Write Cycle(CS Low Holding Consecutive Burst Write)Figure 31. Timing Waveform of Burst Read Stop by CSFigure 32. Timing Waveform of Burst Write Stop by CSFigure 33. Timing Waveform of Burst Read Suspend Cycle

Figure 34. Synch. Burst Read to Asynch. Write(Address Latch Type) Timing WaveformFigure 35. Synch. Burst Read to Asynch. Write(Low ADV Type) Timing Waveform

Figure 36. Asynch. Write(Address Latch Type) to Synch. Burst Read Timing WaveformFigure 37. Asynch. Write(Low ADV Type) to Synch. Burst Read Timing WaveformFigure 38. Synch. Burst Read to Synch. Burst Write Timing WaveformFigure 39. Synch. Burst Write to Synch. Burst Read Timing Waveform

AdvanceUtRAM

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K1B2816B7M

Fig.2 FUNCTIONAL BLOCK DIAGRAM

CLK generator

Precharge circuit.

AdvanceUtRAM

VccVss

Row Addresses

Rowselect

Memory array

I/O0~I/O7

DatacontrollerDatacontrollerDatacontroller

I/O CircuitColumn select

I/O8~I/O15

Column Addresses

CLKADVMRSCSOEWEUBLBWAIT

Control Logic

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K1B2816B7M

POWER UP SEQUENCE

AdvanceUtRAM

After applying VCC upto minimum operating voltage(1.7V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regard-less of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence.1. Apply power.

2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS and MRS high.

Fig.3 POWER UP TIMING

200µs VCC(Min)VCC

Min. 0ns MRS

~≈Min. 200µs ≈CS

Min. 0ns Power Up Mode(Note)

Normal Operation 1. After VCC reaches VCC(Min.), wait 200µs with CS and MRS high. Then the device gets into the normal operation.

Fig.4 STANDBY MODE STATE MACHINES

CS=VIHMRS=VIH

Power On

Initial State(Wait 200µs)

CS=VIL,

WE=VIL, MRS=VIL

MRS Setting

CS=VIL, UB or LB=VILMRS=VIH

Active

VIHS=VIL CS=VIH StandbyMode

MRPARMode

S=MRMRS=VIL DPD Mode

MRS SettingCS=VIL,

WE=VIL, MRS=VIL

MRS=VIH

Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write) and DPD enable. But this defaultmode is not 100% guaranteed so MRS setting sequence is highly recommended after power up or after getting out of DPDmode. Once the device gets out of DPD mode, all the register settings are initialized into the default mode.

For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence.

For entry to DPD mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting hasbeen completed(A4=0). To get out of the DPD mode, drive MRS pin into VIH with wake up sequence(See Page 16).

DPD mode or PAR mode can be selected through Mode Register Set(See Page 10).

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K1B2816B7M

FUNCTIONAL DESCRIPTION

Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)

CSHHLLLLLLLLL

MRSHLHHHHHHHHL

OEX1)X1)HX1)LLLHHHH

WEX1)X1)HX1)HHHLLLL

LBX1)X1)X1)HLHLLHLX1)

UBX1)X1)X1)HHLLHLLX1)

I/O0~7High-ZHigh-ZHigh-ZHigh-ZDoutHigh-ZDoutDinHigh-ZDinHigh-Z

I/O8~15High-ZHigh-ZHigh-ZHigh-ZHigh-ZDoutDoutHigh-ZDinDinHigh-Z

ModeDeselectedDeselectedOutput DisabledOutput DisabledLower Byte ReadUpper Byte ReadWord ReadLower Byte WriteUpper Byte WriteWord WriteMode Register Set

AdvanceUtRAM

PowerStandbyDPD or PARActiveActiveActiveActiveActiveActiveActiveActiveActive

1. X must be low or high state.

2. In asynchronous mode, Clock and ADV are ignored.3. /WAIT pin is High-Z in Asynchronous mode.

Table 4. SYNCHRONOUS BURST READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/1)

CSHHLLLLLLLLLL

MRSHLHHHHHHHHHL

OEX1)X1)HX1)X1)LLLHHHH

WEX1)X1)HX1)HHHHLLLL

LBX1)X1)X1)HX1)LHLLHLX1)

UBX1)X1)X1)HX1)HLLHLLX1)

I/O0~7High-ZHigh-ZHigh-ZHigh-ZHigh-ZDoutHigh-ZDoutDinHigh-ZDinHigh-Z

I/O8~15High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZDoutDoutHigh-ZDinDinHigh-Z

X2)X2)X2)X2)

HHH or or or or

CLKX2)X2)X2)X2)

ADVX2)X2)HH

ModeDeselectedDeselectedOutput DisabledOutput DisabledRead CommandLower Byte ReadUpper Byte ReadWord ReadLower Byte WriteUpper Byte WriteWord WriteMode Register Set

PowerStandbyDPD or PARActiveActiveActiveActiveActiveActiveActiveActiveActiveActive

1. X must be low or high state.

2. X means \"Don’t care\"(can be low, high or toggling).

3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.

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K1B2816B7M

AdvanceUtRAM

Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)

CSHHLLLLLLLLLLL

MRSHLHHHHHHHHHHL

OEX1)X1)HX1)X1)LLLX1)HHHH

WEX1)X1)HX1)HHHHL or X1)X1)X1)L or LBX1)X1)X1)HX1)LHLX1)LHLX1)

UBX1)X1)X1)HX1)HLLX1)HLLX1)

I/O0~7High-ZHigh-ZHigh-ZHigh-ZHigh-ZDoutHigh-ZDoutHigh-ZDinHigh-ZDinHigh-Z

I/O8~15High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZDoutDoutHigh-ZHigh-ZDinDinHigh-Z

H H HHHH

CLKX2)X2)X2)X2)

ADVX2)X2)HH

ModeDeselectedDeselectedOutput DisabledOutput DisabledRead CommandLower Byte ReadUpper Byte ReadWord ReadWrite CommandLower Byte WriteUpper Byte WriteWord WriteMode Register Set

PowerStandbyDPD or PARActiveActiveActiveActiveActiveActiveActiveActiveActiveActiveActive

1. X must be low or high state.

2. X means \"Don’t care\"(can be low, high or toggling).

3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.

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K1B2816B7M

MODE REGISTER SETTING OPERATION

AdvanceUtRAM

UtRAM has two different kinds of mode register setting. One is MRS pin control type and the other is special cycle timing contol type.K1B2816B7M is MRS pin control type device and K1B2816BDM is special cycle timing control type device.

The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Syn-chronous Burst Write mode, Standby mode, Deep Power Down(DPD) mode and Partial Array Refresh(PAR) mode.

Deep Power Down(DPD) mode and Partial Array Refresh(PAR) mode are defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR), Deep Power Down(DPD) mode, Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS, ADV, WE and MRS to VIL and driving OE to VIH during valid address. The mode register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A3, Deep Power Down(DPD) field uses A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Output Impedance uses A16~A17.

Refer to the Table below for detailed Mode Register Setting. A18~A22 addresses are \"Don’t care\" in Mode Register Setting.Table 6. Mode Register Setting according to field of functionAddressFunction

A17~A16Impedance

A15~A14MS

A13WP

A12RFU

A11~A9Latency

A8BT

A7~A5BL

A4DPD

A3PAR

A2PARA

A1~A0PARS

NOTE : Impedance(Output Impedance), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type), BL(Burst Length), DPD(Deep Power Down), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array), PARS(Partial Array Refresh Size), RFU(Reserved for Future Use)Table 7. Mode Register Set

Output Impedance

A17001

A16010WAIT PolarityA1301

WPLow EnableHigh Enable

A1201

ImpedanceFull Drive1/2 Drive1/4 Drive

RFU

RFUMust-A110000

Deep Power DownA401

DPDDPD EnableDPD Disable

Partial Array RefreshA301

PARPAR EnablePAR Disable

A201

A15001

A14010

Mode Select

Async. 4 Page Read / Async. WriteSync. Burst Read / Async. WriteSync. Burst Read / Sync. Burst Write

Latency CountA100011PAR Array

PARABottom ArrayTop Array

A10011

A90101

Latency

3456

PAR SizeA00101

PARSFull Array3/4 Array1/2 Array1/4 ArrayBurst TypeA801

BTLinearInter-A70011

A61101

Burst Length

A50100

BL4 word8 word16 wordFull(256 word)

NOTE : The address bits other than those listed in the table above are reserved.

For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:1.

If the reserved address bits are input, then the mode will be set into the default mode. Each field has its own default mode and these default modes are written in blue-bold in the table above.

Once the device gets out of DPD mode, all the register settings are initialized into the default mode(Full Drive, Async. 4 Page Read / Async. Write mode, DPD enable). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up or after getting out of DPD mode.

DPD mode has a higher priority to PAR mode. So if the PAR mode is required, then the settings should be A4=1 and A3=0. A12 is a reserved bit for future use. A12 must be set as \"0\".

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K1B2816B7M

MRS pin Control Type Mode Register Setting Timing

AdvanceUtRAM

In this device(K1B2816B7M), MRS pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Deep Power Down mode or Partial Array Refresh mode.

To get into the Mode Register Setting, the system must drive MRS pin to VIL and immediately(within 0.5µs) issue a write com-mand(drive CS, ADV and WE to VIL and drive OE to VIH during valid address). If the subsequent write command(WE signal input) is not issued within 0.5µs, then the device might get into the DPD(or PAR) mode.

Fig.5 MODE REGISTER SETTING TIMING(OE=VIH)

CLK

123456710111213

ADV

tWC

Address

tCW

tRWR

UB, LB

tAW

tBW

tWP

tAStMW

tWU

MRS

(MRS SETTING TIMING)1. Clock input is ignored.

Table 8. MRS AC CHARACTERISTICS (VCC=1.7~2.1V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz)

Parameter List

MRS

MRS Enable to Register Write StartEnd of Write to MRS Disable

Symbol

Min

tRWRtMWtWU

500

Speed

Max-500-nsnsnsUnits

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K1B2816B7M

ASYNCHRONOUS OPERATION

Asynchronous 4 Page Read Operation

Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without tog-gling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle

time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation)

Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation.

AdvanceUtRAM

SYNCHRONOUS BURST OPERATION

Burst mode operations enable the system to get high perfor-mance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV(whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low).

For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table \"Mode Register Set\")

Asynchronous Write Operation

Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write opera-tion.) Clock, ADV, WAIT signals are ignored during the asyn-chronous (page) read operation.

Synchronous Burst Read Operation

The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read com-mand, WE should be held in VIH. The multiple clock risings(dur-ing low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD.

Asynchronous Write Operation in Syn-chronous Mode

A write operation starts when CS, WE and UB or LB are driven to VIL under the valid address. Clock input does not have any affect to the write operation(MRS and OE should be driven to VIH during write operation. ADV can be either toggling for address latch or held in VIL). Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation.Fig.6 ASYNCHRONOUS 4-PAGE READ

A22~A2

Synchronous Burst Write Operation

The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS.

Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable)

012345671011121314CLKADV

A1~A0

Addr.

CSUB, LB

Data out

WAIT

UB, LB

Fig.7 ASYNCHRONOUS WRITE

Address

Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable)

CLKADV

Addr.

UB, LB

CSUB, LBWE

Data in

High-Z

Data in

High-Z

Data outWAIT

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K1B2816B7M

SYNCHRONOUS BURST OPERATION TERMINOLOGYClock(CLK)

AdvanceUtRAM

The clock input is used as the reference for synchronous burst read and write operation of UtRAM. The synchronous burst read and write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.

Latency Count

The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency.The supported Latency Count is as follows.Table 9. Latency Count support : 3, 4, 5

Clock FrequencyLatency Count

Table 10. Number of Clocks for 1st Data

Set Latency

# of Clocks for 1st data(Read)# of Clocks for 1st data(Write)Fig.10 Latency Configuration(Read)TUpto 66MHz

4, 5

Upto 54MHz

Upto 40MHz

Latency 3

Latency 4

Latency 5

ClockADVAddressLatency 3Data outLatency 4Data outLatency 5Data outLatency 6Data outDQ1DQ2DQ3DQ4DQ5DQ6DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin.Burst Length

Burst Length identifies how many data the device outputs at an access. The device supports 4 word, 8 word and 16 word burst read or write. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock.

Burst Stop

Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during the burst read opera-tion, then the burst operation will be stopped. During the burst read operation, the new burst operation can not be issued. The new burst operation can be issued only after the previous burst operation is finished.

The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment.

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SYNCHRONOUS BURST OPERATION TERMINOLOGYWAIT Control(WAIT)

AdvanceUtRAM

The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid.

To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable.

For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle.

Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable)0CLK123456710111213ADVCSReadData outWAITWriteData inWAITLatency 5DQ0DQ1DQ2DQ3High-ZLatency 5 D0 D1 D2 D3High-ZBurst Type

The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page.

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Table 11. Burst Sequence

Burst Address Sequence(Decimal)

Start Addr.

Wrap1)

4 word BurstLinear

01234567~1415~255

1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length.

2. Wrap Around : Burst Address continuously wraps around within word boundary until the burst is stopped.

0-1-2-31-2-3-02-3-0-13-0-1-2

Interleave0-1-2-31-0-3-22-3-0-13-2-1-0

8 word BurstLinear0-1-...-5-6-71-2-...-6-7-02-3-...-7-0-13-4-...-0-1-24-5-...-1-2-35-6-...-2-3-46-7-...-3-4-57-0-...-4-5-6

Interleave0-1-2-...-6-71-0-3-...-7-62-3-0-...-4-53-2-1-...-5-44-5-6-...-2-35-4-7-...-3-26-7-4-...-0-17-6-5-...-1-0

16 word BurstLinear0-1-2-...-14-151-2-3-...-15-02-3-4-...-0-13-4-5-...-1-24-5-6-...-2-35-6-7-...-3-46-7-8-...-4-57-8-9-...-5-6

14-15-0-...-12-1315-0-1-...-13-14

Interleave0-1-2-3-4...14-151-0-3-2-5...15-142-3-0-1-6...12-133-2-1-0-7...13-124-5-6-7-0...10-115-4-7-6-1...11-106-7-4-5-2...8-97-6-5-4-3...9-8

14-15-12-...-0-115-14-13-...-1-0

AdvanceUtRAM

Wrap Around2)Full Page(256 word)

Linear0-1-2-...-255-0-1-...1-2-3-...-255-0-1-...2-3-4-...-255-0-1...3-4-5-...-255-0-1-...4-5-6-...-255-0-1-...5-6-7-...-255-0-1-...6-7-8-...-255-0-1-...7-8-9-...-255-0-1-...

14-15-...-255-0-1-...15-16-...-255-0-1-...

255-0-1-...-255-0-1-...

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K1B2816B7M

LOW POWER FEATURES

Deep Power Down(DPD) mode

The deep power down mode disables all refresh related activity. This mode is used when the system does not need to store the data in UtRAM. The data stored in UtRAM will become cor-rupted if DPD mode is executed. The default mode is DPD enabled. But even though DPD mode is enabled through the Mode Register Setting, DPD mode execution is still needed to disable all the refresh related activity. So the normal operation can be executed in DPD enabled mode as long as MRS pin is not driven to low for over 0.5µs.

Wake up sequence is needed for the device to exit from the DPD executed mode. Once the device gets out of DPD excuted mode, the Mode Register Settings are initialized into the default mode so the mode register should be re-written for a proper operation.

Fig.12 DPD MODE EXECUTION and EXIT

200µs≈AdvanceUtRAM

Output Impedance Matching

The optimization of output driver strength is possible throughthe mode register setting to adjust for the different data load-ings.

Through this output impedance matching, the device can mini-mize the noise generated on the data bus during read opera-tion.

The device supports full drive, 1/2 drive and 1/4 drive.

Partial Array Refresh(PAR) mode

The PAR mode enables the user to specify the active memory array size. UtRAM consists of 4 blocks and user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory array through Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not going to be refreshed and so the previously stored data will get lost.To set PAR mode, DPD mode should be disabled(A4=1). Even though PAR mode is enabled through the Mode Register Set-ting, PAR mode execution by MRS pin is still needed.

The normal operation can be executed even in refresh-disabled array as long as MRS pin is not driven to low for over 0.5µs.Driving MRS pin to high makes the device to get back to the normal operation mode from PAR executed mode,

Refer to Fig.13 and Table 12 for PAR operation and PAR address mapping.

Fig.13 PAR MODE EXECUTION and EXIT

0.5µsMRS

Normal OperationMODE

SuspendWake upNormal OperationDPD modeCS

≈Internal TCSR

The internal Temperature Compensated Self Refresh(TCSR) feature is a very useful tool for reducing standby current in room temperature(below 40°C). DRAM cell has weak refresh charac-teristics in higher temperature. So high temperature requires more refresh cycles, which lead to standby current increase.Without internal TCSR, the refresh cycle should be set as worst condition so as to cover high temperature(85°C) refresh char-acteristics. But with internal TCSR, the refresh cycle below 40°C can be optimized, so the standby current in room temper-ature can be highly reduced. This feature is really beneficial to mobile phone because most of mobile phones are used at below 40°C in the phone standby mode.

MRS

Normal OperationMODE

0.5µs≈SuspendPAR mode≈Normal OperationCS

Table 12. PAR MODE CHARACTERISTIC

Power ModeStandby(Full Array)Partial Refresh(3/4 Block)Partial Refresh(1/2 Block)Partial Refresh(1/4 Block)

Deep Power Down

Address(Bottom Array)2)000000h ~ 7FFFFFh000000h ~ 5FFFFFh000000h ~ 3FFFFFh000000h ~ 1FFFFFh000000h ~ 7FFFFFh

Address(Top Array)2)000000h ~ 7FFFFFh200000h ~ 7FFFFFh400000h ~ 7FFFFFh600000h ~ 7FFFFFh000000h ~ 7FFFFFh

Memory Cell DataValid1)Valid1)Valid1)Valid1)Invaild

Standby Current

(µA, Max)

TBDTBDTBDTBDTBD

Wait Time(µs)

0000200

1. Only the data in the refreshed block are valid

2. PAR Array can be selected through Mode Register Set(See Page 10).

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K1B2816B7M

Table 13. PRODUCT LIST

Industrial Temperature Products(-40~85°C)

Part Name

K1B2816B7M

Function

1.8V, 70ns, 66MHz

AdvanceUtRAM

Table 14. ABSOLUTE MAXIMUM RATINGS1)

Item

Voltage on any pin relative to VssPower supply voltage relative to VssPower DissipationStorage temperatureOperating Temperature

SymbolVIN, VOUT

VCCPDTSTGTA

Ratings-0.2 to VCC+0.3V-0.2 to 2.5V

1.0-65 to 150-40 to 85

UnitVVW°C°C

1. Stresses greater than those listed under \"Absolute Maximum Ratings\" may cause permanent damage to the device. Functional operation should berestricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-ability.

Table 15. RECOMMENDED DC OPERATING CONDITIONS1)

Item

Power supply voltageGround

Input high voltageInput low voltage

1. TA=-40 to 85°C, otherwise specified.

2. Overshoot: VCC+1.0V in case of pulse width ≤20ns.3. Undershoot: -1.0V in case of pulse width ≤20ns.

4. Overshoot and undershoot are sampled, not 100% tested.

SymbolVCCVssVIHVIL

Min1.701.5-0.23)

Typ1.90--

Max2.10VCC+0.22)

0.4

UnitVVVV

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Table 16. CAPACITANCE1)(f=1MHz, TA=25°C)

Item

Input capacitanceInput/Output capacitance

1. Capacitance is sampled, not 100% tested.

AdvanceUtRAM

SymbolCINCIO

Test Condition

VIN=0VVIO=0V

Min--

Max810

UnitpFpF

Table 17. DC AND OPERATING CHARACTERISTICS

Item

Input Leakage CurrentOutput Leakage CurrentAverage Operating Current

Output Low VoltageOutput High VoltageStandby Current(CMOS)

Symbol

Test Conditions

VIN=Vss to VCC

CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCCycle time=Min, IIO=0mA, 100% duty, CS=VIL, MRS=VIH, VIN=VIL or VIHIOL=0.1mAIOH=-0.1mA

CS≥VCC-0.2V, MRS≥VCC-0.2V, Other inputs=Vss to VCC

< 45°C< 85°C3/4 Block

< 45°C

1/2 Block1/4 Block3/4 Block

< 85°C

1/2 Block1/4 Block

MRS≤0.2V, CS≥VCC-0.2VOther inputs=Vss to VCC

Min-1-1--1.4---------

Typ--------------

Max11TBD0.2-TBDTBDTBDTBDTBDTBDTBDTBDTBD

UnitµAµAmAVVµAµAµA

ILIILOICC2VOLVOHISB1

Partial Refresh CurrentISBP1)

µA

Deep Power DownISBDMRS≤0.2V, CS≥VCC-0.2V, Other inputs=Vss to VCCµA

1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).

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AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCC Output load: CL=30pF

Dout

AdvanceUtRAM

Figure 14. AC Output Load Circuit CL

1. Including scope and jig capacitance

Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.1V, TA=-40 to 85°C)

Parameter List

Read Cycle TimePage Read Cycle TimeAddress Access TimePage Access TimeChip Select to Output

Async. (Page)Read

Output Enable to Valid OutputUB, LB Access TimeChip Select to Low-Z OutputUB, LB Enable to Low-Z OutputOutput Enable to Low-Z OutputChip Disable to High-Z OutputUB, LB Disable to High-Z OutputOutput Disable to High-Z OutputOutput Hold Write Cycle Time

Chip Select to End of WriteADV Minimum Low Pulse Width

Address Set-up Time to Beginning of WriteAddress Set-up Time to ADV FallingAddress Hold Time from ADV Rising

Async.Write

CS Setup Time to ADV RisingAddress Valid to End of WriteUB, LB Valid to End of WriteWrite Pulse WidthWE High Pulse WidthWrite Recovery TimeWE Low to Read Latency Data to Write Time OverlapData Hold from Write Time

1. tWP(min)=70ns for continuous write operation over 50 times.

Symbol

Min

tRCtPCtAAtPAtCOtOEtBAtLZtBLZtOLZtCHZtBHZtOHZtOHtWCtCWtADVtAStAS(A)tAH(A)tCSS(A)tAWtBWtWPtWHPtWRtWLRLtDWtDH

7025-----1055000370607007106060501)5 ns01300

Speed

Max--7020703535---777-----------Latency-1 clock

----

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns-nsclocknsns

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ASYNCHRONOUS READ TIMING WAVEFORM

Fig.15 TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE (MRS=VIH, WE=VIH, WAIT=High-Z)tRC

Address

AdvanceUtRAM

tAA

tOH

tCO

tCHZ

tBA

UB, LB

tBHZ

tOE

Data outHigh-Z

tLZ

tOLZtBLZ

Data Valid

tOHZ(ASYNCHRONOUS READ CYCLE)

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.

3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored.

Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS

Symbol

Min

tRCtAAtCOtBAtOEtOH

70----3

Speed

Max-70703535-nsnsnsnsnsns

tOLZtBLZtLZtCHZtBHZtOHZ

Units

Symbol

Min5510000

Speed

Max---777

nsnsnsnsnsnsUnits

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K1B2816B7M

ASYNCHRONOUS READ TIMING WAVEFORM

Fig.16 TIMING WAVEFORM OF PAGE READ CYCLE(MRS=VIH, WE=VIH, WAIT=High-Z)tRC

A22~A2

tAA

A1~A0

ValidAddress

AdvanceUtRAM

tOHtPC

tCO

tBA

UB, LB

tBHZ

tOE

tLZHigh Z

tOLZtBLZ

tPA

DataValid

tCHZtOHZData out

(ASYNCHRONOUS 4 PAGE READ CYCLE)

3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored.

Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS

Symbol

Min

tRCtAAtPCtPAtCOtBAtOE

70-25----Speed

Max-70-20703535

nsnsnsnsnsnsns

tOHtOLZtBLZtLZtCHZtBHZtOHZ

Units

Symbol

Min35510000

Speed

Max----777

nsnsnsnsnsnsnsUnits

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ASYNCHRONOUS WRITE TIMING WAVEFORM

Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)

tWC

Address

tCW

tAW

tBW

tWP

tAS

Data in

High-Z

tDW

Data Valid

tDH

High-Z

tWR

AdvanceUtRAM

UB, LB

Data outHigh-ZHigh-Z

(ASYNCHRONOUS WRITE CYCLE - WE Controlled)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UBor LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transitionwhen CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.

Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled)

Symbol

Min

tWCtCWtAWtBWtWP

70606060501)

Speed

Max-----nsnsnsnsns

tAStWRtDWtDH

Units

Symbol

Min00300

Speed

Max----nsnsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM

Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)

tWC

Address

tCW

tAW

UB, LB

tBW

tAS

tWP

tDW

Data in

Data Valid

tDHtWR

AdvanceUtRAM

Data outHigh-ZHigh-Z

(ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.

Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled)

Symbol

Min

tWCtCWtAWtBWtWP

70606060501)

Speed

Max-----nsnsnsnsns

tAStWRtDWtDH

Units

Symbol

Min00300

Speed

Max----nsnsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

AdvanceUtRAM

Fig.19 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)

0CLK

tADVADVAddressCS UB, LB

tWLRLWE

tASData in

Read Latency 5Data out

High-ZHigh-ZtAS(A)tAH(A)Valid12345671011121314tCSS(A)tCWtAWtBWtWPtDWData ValidtDH(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE Controlled)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UBor LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition whenCS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW.3. tCW is measured from the CS going low to the end of write.

4. tBW is measured from the UB and LB going low to the end of write.

5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.

Table 23. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, WE Controlled)

Symbol

Min

tADVtAS(A)tAH(A)tCSS(A)tCWtAW

707106060

Speed

Max------nsnsnsnsnsns

tBWtWPtWLRLtAStDWtDH

Units

Symbol

Min60501)10300

Speed

Max------nsnsclocknsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

AdvanceUtRAM

Fig.20 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)

0CLK

tADVADVAddressCS UB, LB

tASWEData in

Read Latency 5Data out

High-ZHigh-ZtWLRLtAS(A)tAH(A)Valid12345671011121314tCSS(A) tCWtAWtBWtWPtDWData ValidtDH(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UBor LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition whenCS goes or and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW.3. tCW is measured from the CS going low to the end of write.

4. tBW is measured from the UB and LB going low to the end of write.

5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.

Table 24. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, UB & LB Controlled)

Symbol

Min

tADVtAS(A)tAH(A)tCSS(A)tCWtAW

707106060

Speed

Max------nsnsnsnsnsns

tBWtWPtWLRLtAStDWtDH

Units

Symbol

Min60501)10300

Speed

Max------nsnsclocknsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

AdvanceUtRAM

Fig.21 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)

0CLKADV

tWCAddress

tCWCSUB, LB

tWLRLWEData in

Read Latency 5Data out

High-ZHigh-ZtAStDHtDWData ValidtAWtBWtWPtWR12345671011121314(LOW ADV TYPE WRITE CYCLE - WE Controlled)

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.

Table 25. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, WE Controlled)

Symbol

Min

tWCtCWtAWtBWtWP

70606060501)

Speed

Max-----nsnsnsnsns

tWLRLtAStWRtDWtDH

Units

Symbol

Min100300

Speed

Max-----clocknsnsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

AdvanceUtRAM

Fig.22 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)

0CLKADV

tWCAddress

tCWCSUB, LBWE

tDHtDWData ValidRead Latency 5Data out

High-ZHigh-ZtAWtBWtAStWLRLtWPtWR12345671011121314Data in

(LOW ADV TYPE WRITE CYCLE - UB & LB Controlled)

3. tAS is measured from the address valid to the beginning of write.

Table 26. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, UB & LB Controlled)

Symbol

Min

tWCtCWtAWtBWtWP

70606060501)

Speed

Max-----nsnsnsnsns

tWLRLtAStWRtDWtDH

Units

Symbol

Min100300

Speed

Max-----clocknsnsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE

AdvanceUtRAM

Fig.23 TIMING WAVEFORM OF MULTIPLE WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)

CLK

ADV

tWC

Address

tAWtCW

tWR

tAWtCW

tWR

tWC

tBW

UB, LB

tWP

tAS

tDHtDW

Data Valid

tWHP

tAS

tBW

tWP

Data inData out

tDHtDW

Data Valid

High-ZHigh-Z

(LOW ADV TYPE MULTIPLE WRITE CYCLE)

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

5. Clock input does not have any affect to the asynchronous multiple write operation if tWHP is shorter than (Read Latency - 1) clockduration.

6. tWP(min)=70ns for continuous write operation over 50 times.

Table 27. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type Multiple Write, WE Controlled)

Symbol

Min

tWCtCWtAWtBWtWP

70606060501)

Speed

Max-----nsnsnsnsns

tWHPtAStWRtDWtDH

Units

Symbol

Min5ns00300

Speed

MaxLatency-1 clock

-----nsnsnsnsUnits

1. tWP(min)=70ns for continuous write operation over 50 times.

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AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Test Input/Output Reference)

Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns

Input and output reference voltage: 0.5 x VCC Output load: CL=30pF

AdvanceUtRAM

Figure 24. AC Output Load Circuit Vtt=0.5 x VDDQ50ΩDoutZ0=50Ω 30pFTable 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.1V, TA=-40 to 85°C, Maximum Main Clock Fre-quency=66MHz)

Parameter ListClock Cycle TimeBurst Cycle Time

ADV Minimum Low Pulse Width

Address Set-up Time to ADV Falling(Burst)Address Hold Time from ADV Rising(Burst)ADV Setup Time

Burst

Operation (Common)

ADV Hold Time

CS Setup Time to Clock Rising(Burst)Burst End to New ADV FallingCS Low Hold Time from ClockCS High Pulse WidthADV High Pulse WidthChip Select to WAIT LowADV Falling to WAIT LowClock to WAIT High

Chip De-select to WAIT High-ZUB, LB Enable to End of Latency ClockOutput Enable to End of Latency ClockUB, LB Valid to Low-Z OutputOutput Enable to Low-Z Output

Burst ReadOperation

Latency Clock Rising Edge to Data OutputOutput Hold

Burst End Clock to Output High-ZChip De-select to Output High-ZOutput Disable to Output High-ZUB, LB Disable to Output High-ZWE Set-up Time to Command ClockWE Hold Time from Command ClockWE High Pulse Width

Burst WriteOperation

UB, LB Set-up Time to ClockUB, LB Hold Time from ClockByte Masking Set-up Time to ClockByte Masking Hold Time from ClockData Set-up Time to ClockData Hold Time from Clock

Symbol

Min

TtBCtADVtAS(B)tAH(B)tADVStADVHtCSS(B)tBEADVtCSLHtCSHPtADHPtWLtAWLtWHtWZtBELtOELtBLZtOLZtCDtOHtHZtCHZtOHZtBHZtWEStWEHtWHPtBStBHtBMStBMHtDStDH

15-7075757755----1155-3----555557750

Speed

Max2002500----------101077----10-10777---------

UnitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsClockClocknsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

- 29 -

Revision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST OPERATION TIMING WAVEFORM

Fig.25 TIMING WAVEFORM OF BASIC BURST OPERATION [Latency=5,Burst Length=4](MRS=VIH)

AdvanceUtRAM

TCLK

1234567101112131415

tADVHtADVSADV

tADVtAS(B)tAH(B)tBEADVtBEADVAddressValidDon’t CaretCSS(B)CS

tBCData outUndefinedDQ0DQ1DQ2DQ3Data in D0 D1 D2 D3Burst Command ClockBurst Read End ClockBurst Write End Clock

Table 29. BURST OPERATION AC CHARACTERISTICS

Symbol

Min

TtBCtADVtADVStADVH

15-757

Speed

Max2002500---nsnsnsnsns

tAS(B)tAH(B)tCSS(B)tBEADV

Units

Symbol

Min0757

Speed

Max----nsnsnsnsUnits

- 30 -

∼Valid D0 Revision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST READ TIMING WAVEFORM

AdvanceUtRAM

Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Read

TCLK

tADVHtADVSADV

tAS(B)Address

Valid1234567101112131415

tADVtAH(B)Don’t CaretBEADVtCSS(B)CS

tBCtCSHPtBELLB, UB

tBLZOE

tOLZLatency 5Data out

tWLWAIT

High-ZtWHtOELtCDUndefinedtOHDQ0DQ1DQ2DQ3tWZ(SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)

Symbol

Min

tCSHPtBELtOELtBLZtOLZtHZtCHZ

51155--Speed

Max-----107

nsclockclocknsnsnsns

tOHZtBHZtCDtOHtWLtWHtWZ

Units

Symbol

Min---3---Speed

Max7710-1077

nsnsnsnsnsnsnsUnits

- 31 -

∼∼ValidtBHZtOHZtCHZtHZtWHtWLRevision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST READ TIMING WAVEFORM

AdvanceUtRAM

Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Read

TCLK

tADVHtADVSADV

tAS(B)Address

Valid1234567101112131415

tADVtAH(B)Don’t CaretBEADVtCSS(B)CS

tBELLB, UB

tBLZOE

tOLZLatency 5Data out

tWLWAIT

High-ZtOELtBCtCDUndefinedtOHDQ0DQ1DQ2DQ3tWH(SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.

4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.5. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

Symbol

Min

tBELtOELtBLZtOLZtHZ

1155-Speed

Max----10

clockclocknsnsns

tCDtOHtWLtAWLtWH

Units

Symbol

Min-3---Speed

Max10-10107

nsnsnsnsnsUnits

- 32 -

∼∼ValidtHZtAWLtWHRevision 0.1

November 2003

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K1B2816B7M

SYNCHRONOUS BURST READ TIMING WAVEFORM

AdvanceUtRAM

Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - Last Data Sustaining

TCLK

tADVHtADVSADV

tAS(B)Address

Valid12345671011121314

tADVtAH(B)Don’t CaretCSS(B)CS

tBELLB, UB

tBLZtOELOE

tOLZLatency 5Data out

tWLWAIT

High-ZtBCtCDUndefinedtOHDQ0DQ1DQ2DQ3tWH(SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining)1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.3. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining)

Symbol

Min

tBELtOELtBLZtOLZ

1155

Speed

Max----clockclocknsns

tCDtOHtWLtWH

Units

Symbol

Min-3--Speed

Max10-107

nsnsnsnsUnits

- 33 -

Revision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST WRITE TIMING WAVEFORM

AdvanceUtRAM

Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Write

TCLK

tADVHtADVSADV

tAS(B)Address

tCSS(B)CS

tBStBHLB, UB

tWEHWE

tWEStDSLatency 5Data in

tWLWAIT

High-ZtWHtDH D0 D1 D2tDH D3tWZtWLtWHLatency 5 D0 tWHPtBMStBMHValid123456710111213

tADVtAH(B)Don’t CaretBEADVtBCtCSHP(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 4. DQ2 is masked by UB and LB.

5. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst)

Symbol

Min

tCSHPtBStBHtBMStBMHtWEStWEH

5557755

Speed

Max-------nsnsnsnsnsnsns

tWHPtDStDHtWLtWHtWZ

Units

Symbol

Min550---Speed

Max---1077

nsnsnsnsnsnsUnits

- 34 -

∼ValidRevision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST WRITE TIMING WAVEFORM

AdvanceUtRAM

Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Write

TCLK

tADVHtADVSADV

tAS(B)Address

Valid123456710111213

tADVtAH(B)Don’t CaretBEADVValidtCSS(B)CS

tBCtBStBHtBMStBMHLB, UB

tWEHWE

tWEStDSLatency 5Data in

tWLWAIT

High-ZtWHtDH D0 D1 D2tDH D3tAWLtWHLatency 5 D0 tWHP(SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 4. DQ2 is masked by UB and LB.

5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.6. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst)

Symbol

Min

tBStBHtBMStBMHtWEStWEH

557755

Speed

Max------nsnsnsnsnsns

tWHPtDStDHtWLtAWLtWH

Units

Symbol

Min550---Speed

Max---10107

nsnsnsnsnsnsUnits

- 35 -

∼Revision 0.1November 2003

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K1B2816B7M

SYNCHRONOUS BURST READ STOP TIMING WAVEFORMAdvanceUtRAM

Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

TCLK

tADVHtADVSADV

tAS(B)Address

Valid12345671011121314

tADVtAH(B)Don’t CaretBEADVtCSS(B)CS

tBELLB, UB

tBLZOE

tOLZLatency 5Data

tWLWAIT

High-ZtWHtOELtCDUndefinedtCSHPtCSLHtOHDQ0DQ1tCHZtWZHigh-Z(SYNCHRONOUS BURST READ STOP TIMING)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. The burst stop operation should not be repeated for over 2.5µs.

Table 35. BURST READ STOP AC CHARACTERISTICS

Symbol

Min

tCSLHtCSHPtBELtOELtBLZtOLZ

751155

Speed

Max------nsnsclockclocknsns

tCDtOHtCHZtWLtWHtWZ

Units

Symbol

Min-3----Speed

Max10-71077

nsnsnsnsnsnsUnits

- 36 -

∼∼ValidtWLRevision 0.1

November 2003

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K1B2816B7M

SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORMAdvanceUtRAM

Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)

TCLK

tADVHtADVSADV

tAS(B)Address

Valid123456710111213

tADVtAH(B)Don’t CaretBEADVValidtCSS(B)CS

tBStBHLB, UB

tWEHWE

tWEStDSLatency 5Data in

tWLWAIT

High-ZtWH D0tDH D1tCSLHtCSHPtWHPtWZ(SYNCHRONOUS BURST WRITE STOP TIMING)

1. The new burst operation can be issued only after the previous burst operation is finished.2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. The burst stop operation should not be repeated for over 2.5µs.

Table 36. BURST WRITE STOP AC CHARACTERISTICS

Symbol

Min

tCSLHtCSHPtBStBHtWEStWEH

755555

Speed

Max------nsnsnsnsnsns

tWHPtDStDHtWLtWHtWZ

Units

Symbol

Min550---Speed

Max---1077

nsnsnsnsnsnsUnits

- 37 -

∼∼Latency 5 D0tWLHigh-ZtWH D1 D2Revision 0.1

November 2003

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K1B2816B7M

SYNCHRONOUS BURST READ SUSPEND TIMING WAVEFORM

AdvanceUtRAM

Fig.33 TIMING WAVEFORM OF BURST READ SUSPEND CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)

TCLK

tADVHtADVSADV

tAS(B)Address

Valid12345671011

∼∼tADVtAH(B)Don’t CaretCSS(B)CS

tBELLB, UB

tBLZOE

tOLZLatency 5Data out

tWLWAIT

High-ZtWHtOELtBCtCDUndefinedtOHZDQ0DQ1tOLZHigh-ZDQ1tOHDQ2DQ3tHZtWZ(SYNCHRONOUS BURST READ SUSPEND CYCLE)

1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high drives data out to high-Z. If clock input is resumed, the suspended data will be out first.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z. If OE stays low during suspend period, the previous data will be sustained.4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 37. BURST READ SUSPEND AC CHARACTERISTICS

Symbol

Min

tBELtOELtBLZtOLZtCDtOH

1155-3

Speed

Max----10-clockclocknsnsnsns

tHZtOHZtWLtWHtWZ

Units

Symbol

Min-----Speed

Max1071077

nsnsnsnsnsUnits

- 38 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

AdvanceUtRAM

Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0TCLK

tADVSADV

tAS(B)Address

Valid1234567101112131415161718192021

tADVHtADVtAH(B)Don’t CaretBEADVtAS(A)tAH(A)ValidtCSS(B)CS

tBCtCSS(A)tWLRLtAWtCWtWPWE

tAStOELOE

tBELLB, UB

tDWData in

Latency 5Data out

High-ZtWLWAIT

High-ZtWHHigh-ZRead Latency 5(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clockin write timing is just a reference to WE low going for proper write operation.

tBWtDHData ValidtCDtOHDQ0DQ1DQ2DQ3tHZHigh-ZtWZTable 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS

Symbol

Min

tBEADV

Speed

Max-ns

tWLRL

Units

Symbol

Min1

Speed

Max-clockUnits

- 39 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

AdvanceUtRAM

Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

1TCLK

tADVSADV

tAS(B)AddressValid234567101112131415161718192021tADVHtADVtAH(B)Don’t CaretBEADVValid AddresstCSS(B)CS

tBCtAWtCWtWLRLtWRtWPWE

tOELOE

tBELLB, UB

tAStBWtDWtDHData in

Latency 5Data outHigh-ZtWLWAIT

High-ZtWHHigh-ZRead Latency 5tCDtOHDQ0DQ1DQ2DQ3Data ValidtHZHigh-ZtWZ(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.

Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS

Symbol

Min

tBEADV

Speed

Max-ns

tWLRL

Units

Symbol

Min1

Speed

Max-clockUnits

- 40 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

AdvanceUtRAM

Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0CLK

tADVSADV

tAS(A)AddressValid12345671011T121314151617181920

tADVHtADVtAH(A)Don’t CaretAH(B)tAS(B)ValidDon’t CaretCSS(A)CS

tAWtCWtWLRLtCSS(B)tBCWE

tAStWPtOELOE

tBWLB, UB

tDWData in

tDHtBELData ValidLatency 5tCDtWHtOHDQ0DQ1DQ2DQ3tHZData outHigh-ZRead Latency 5High-ZtWLtWZWAIT

(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.

Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS

Symbol

Min

tWLRL

Speed

Max-clockUnits

Symbol

Min

Speed

Max

Units

- 41 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

AdvanceUtRAM

Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0CLK

tADHPADV

tWCAddressValid12345671011T121314151617181920

tADVStADVHtAH(B)tAS(B)ValidDon’t CaretAWtCWCS

tWLRLWE

tAStWPtWRtCSS(B)tBCtOELOE

tBWtDWData in

tDHtBELLB, UB

Data ValidLatency 5tCDtOHDQ0DQ1DQ2DQ3tHZData outHigh-ZtWLtWHtWZWAITHigh-ZRead Latency 5(SYNCHRONOUS BURST READ CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock)

/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)

1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.

Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS

Symbol

Min

tWLRL

Speed

Max-clock

tADHP

Units

Symbol

Min5

Speed

Max-nsUnits

- 42 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0TCLK

tADVSADV

tAS(B)Address

ValidAdvanceUtRAM

1234567101112131415161718192021

tADVHtBEADVtADVtAH(B)Don’t CaretAS(B)ValidtADVtAH(B)tCSS(B)CS

tBCtWEStCSS(B)tBCtWEHWE

tOELOE

tBELLB, UB

Latency 5Data in

Latency 5Data out

tWLWAIT

High-ZHigh-ZtWHtCDHigh-ZtOHDQ0DQ1DQ2DQ3 D0 D1 D2tBStBHtDS D3tDHtHZHigh-ZtWLtWHtWZtWZ(SYNCHRONOUS BURST READ & WRITE CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS

Symbol

Min

tBEADV

Speed

Max-nsUnits

Symbol

Min

Speed

Max

Units

- 43 -

Revision 0.1November 2003

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K1B2816B7M

TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE

Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM

[Latency=5, Burst Length=4](MRS=VIH)

0TCLK

tADVSADV

tAS(B)Address

ValidAdvanceUtRAM

1234567101112131415161718192021

tADVHtBEADVtADVtAH(B)Don’t CaretAS(B)ValidtADVtAH(B)tCSS(B)CS

tWEStWEHWE

tBCtCSS(B)tBCtOELOE

tBStBHLB, UB

Latency 5Data in

D0 D1 D2tBELtDS D3tDHHigh-ZLatency 5tCDtWHtOHDQ0DQ1DQ2DQ3tHZData out

tWLWAIT

High-ZtWHHigh-ZtWZtWL(SYNCHRONOUS BURST READ & WRITE CYCLE)

1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met.

3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS

Symbol

Min

tBEADV

Speed

Max-nsUnits

Symbol

Min

Speed

Max

Units

- 44 -

Revision 0.1November 2003

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K1B2816B7M

PACKAGE DIMENSION

AdvanceUtRAM

TBD

- 45 -

Revision 0.1November 2003

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