Arrangement and construction of an output control

专利名称：Arrangement and construction of an output

control circuit in a semiconductor memorydevice

发明人：Takayasu Sakurai申请号：US07/274594申请日：19881122公开号：US04974203A公开日：19901127

摘要：A semiconductor memory device includes output control circuits which arelocated adjacent to column sense amplifiers and output transistors which are located at adistance from the output control circuits. The wiring length of a first wiring from thecolumn sense amplifiers to the output control circuits is set to be shorter than the wiringlength of a second wiring from the output control circuits to the output transistors. Thesecond wiring has a parasitic capacitance at least five times the parasitic capacitance ofthe first wiring.

申请人：KABUSHIKI KAISHA TOSHIBA

代理机构：Finnegan, Henderson, Farabow, Garrett, and Dunner

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