verilog程序题详解

1⽤阻塞⽅式设计⼀个2选1的多路选择器module

mux2_1(ina,inb,sel,out);input ina,inb;input sel;output out;reg out;

always@(sel or ina or inb) case(sel)1'b1:out=ina;default:out=inb;endcaseendmodule

2 设计⼀个8位全加器module

adder7(ina,inb,ci,sum,co); input[7:0] ina,inb;input ci;output[7:0]sum;output co;reg[7:0]sum;reg[4:0] carry;genvar i;

generate for(i=0;i<4;i=i+1) begin:r_loopalways@(ina[i] or inb[i] or carry[i])begincarry[0]=ci;

sum[i]=ina[i]^inb[i]^carry[i]; carry[i+1]=ina[i]&inb[i]|ina[i ]&carry[i]|inb[i]&carry[i]; endendendgenerate

assign co=carry[4]; endmodule

3 同步复位的4位计数器module count4(clk,nrst,out); input clk,nrst;output[4:0] out;reg[4:0] out;

always@(posedge clk) if(!nrst)out<=4'b0;else

out<=out+4'b1;endmodule

4 ⽤case语句设计⼀个4选1的数据选择器module

mux4_1(en ,in1 ,in2 ,in3 ,in4,sel ,out );input en ;input [7:0]in1 ,in2 ,in3 ,in4 ;input [1:0] sel ;output [7:0] out ;reg [7:0] out ;always @(sel or enor in4 or in1 or in2 orin3 )beginif (en == 0) out= {8{1'b0}};elsecase (sel )0 : out = in1 ;1 : out = in2 ;2 : out = in3 ;3 : out = in4 ;

default : out ={8{1'b0}};endcaseendendmodule

5 设计⼀个8-3优先编码器module

encoder83(in,outcode);output[2:0] outcode;input [7:0] in;function[2:0] code;input[7:0] ina;if(ina[0])code=3'b000;

else if(ina[1]) c ode=3'b001;else if(ina[2]) c ode=3'b010;else if(ina[3]) c ode=3'b011;else if(ina[4]) c ode=3'b100;else if(ina[5])code=3'b101;

else if(ina[6]) c ode=3'b110;else if(ina[7]) c ode=3'b111;else code=3'bx;endfunction

assign outcode=code(in);endmodule

module bianma83(a,b);input [7:0] a;output [2:0] b;reg [2:0] b;always @ (a)begincasex(a)

8'b00000001:b=3'b000;8'b0000001x:b=3'b001;8'b000001xx:b=3'b010;8'b00001xxx:b=3'b011;8'b0001xxxx:b=3'b100;8'b001xxxxx:b=3'b101;8'b01xxxxxx:b=3'b110;8'b1xxxxxxx:b=3'b111;default:b=3'bx;

endcaseendendmodule

6.设计⼋功能的算术运算单元(ALU)，其输⼊信号a和b均为4位，功能选择信号select为3位．输出信号out为8位。算术运算单元alu所执⾏的操作与select信号有关，具体关系见下表。module alu(a,b,sel,out);input a,b;input[3:0]sel;output[3:0] out;reg[3:0]out;

always@(sel or a or b )case(sel)3'b000:out=a;3'b001:out=a+b;3'b010:out=a-b;3'b011:out=a*b;

3'b100:out=(a>b)?a:b;/*if(a> b)out=a;else out=b;*/3'b101:out=(a3'b110:out=a<<3;

3'b111:out=a>>3; default: out=4'bx; endcaseEndmodule

module fiv4(clk,rst_n,o_clk);input clk,rst_n;output o_clk;reg o_clk;reg [1:0]cnt;

always @(posedge clk or negedge rst_n)beginif(!rst_n)cnt<=0;

else if(cnt==3)cnt<=0;elsecnt<=cnt+1;end

always @(posedge clk or negedge rst_n)beginif(!rst_n)o_clk<=0;else if(cnt<2)o_clk<=1;elseo_clk<=0;endEndmodule

1 ⽤组合逻辑设计ROM modulerom(wr,rd,cs,addr,data);parameter imgw=256,imgh=256;parameter wid=7;parameteraddresswid=17;input wr,rd,cs;input [addresswid-1:0]addr;

inout [wid:0] data;reg [wid:0]ram[0:imgw*imgh];always @(cs or wr oraddr)beginif (!cs && !wr)ram[addr]=data;end

assign data = (!cs&& !rd) ? ram[addr]:

{(wid+1){1'bz}};endmodule

2 设计⼀个2-4的译码器module 2_4 (clk, rst_n,2_data,4_data);input clk;input rst_n;input [1:0] 2_data;output [3:0] 4_data;always@(posedge clk,negedge rst_n)beginif (!rst_n)begin2_data<= 0;4_data<= 0;endelse

case (2_data)00 :

4_data<=4'b0001;01 :

4_data<=4'b0010;10:

4_data<=4'b0100;11 :

4_data<=4'b1000;default :

4_data<=4'b0000;endcaseendendmodule

3 使⽤always语句描述JK触发器，上升沿触发，带有同步清零功能。时钟上升沿

功能表如下：module

JK_FF(CLK,J,K,Q,RS,SET);input CLK,J,K,SET,RS;output Q;reg Q;

always @(posedge CLK ornegedge RS or negedge SET)begin

if(!RS) Q <= 1'b0;else if(!SET) Q <= 1'b1;elsecase({J,K})2'b00 : Q <= Q;2'b01 : Q <= 1'b0;2'b10 : Q <= 1'b1;2'b11 : Q <= ~Q;default: Q<= 1'bx;endcaseendendmodule

4 ⽤verilog代码，分别实现下图电路结构，module

blocking( sel,clk,ina,inb,inc,qout);

input clk,sel,ina,inb,inc;output qout;reg qout,w1;

always@(posedge clk)beginw1=ina|inb;if(sel)qout=w1&inc;else

qout=inc;endendmodulemodule

nonblocking( sel,clk,ina,inb,i nc,qout);input clk,sel,ina,inb,inc; output qout;reg qout,w1;

always@(posedge clk) beginw1<=ina|inb;if(sel)

qout<=w1&inc;elseqout<=inc;endendmodule

5 按照下图系统的结构，⽤verilog代码实现module

hello(ain,bin,sel,clock,rst_n, outa,outb);input[1:0] ain,bin;input sel;input clock;input rst_n;output outa,outb;reg[1:0] result;wire eq0,eq1,eq2,eq3;wire nora,norb;reg outa,outb;

always@(ain or bin or sel) beginif(!sel)result<=ain;elseresult<=bin;end

always@(result)begin

case(result)

2'b00:{eq3,eq2,eq1,eq0}=4'b 0001;2'b01:{eq3,eq2,eq1,eq0}=4'b0010;

2'b10:{eq3,eq2,eq1,eq0}=4'b0100;

2'b11:{eq3,eq2,eq1,eq0}=4'b1000;default:;endcaseend

always@(posedge clock ornegedge rst_n)beginif(!rst_n)outa<=0;elseouta<=nora;end

always@(posedge clock ornegedge rst_n)beginif(!rst_n)outb<=0;elseoutb<=norb;end

assign nora=eq0^eq1;assign norb=eq2^eq3;endmodule

6 设计⼀个4位脉动进位计数器module

ripple_carry_counter(q,clk,rst);

input clk,rst;output[3:0] q;tff t0(q[0],clk,rst);tff t1(q[1],clk,rst);tff t2 (q[2],clk,rst);tff t3(q[3],clk,rst);endmodulemodule tff(q,clk,rst);input clk,rst;output q;wire d;

dff d1(q,d,clk,rst);not n1(d,q);endmodule

module dff(q,d,clk,rst);input d,clk,rst;output q;reg q;

always@(negedge clk orposedge rst)if(rst)q<=0;elseq<=d;endmodule

1将1个200kHz 时钟做2分频、4 分频、8 分频，要求分频后的3 个时钟同相，⽽且与源时钟近似同相。并编写测试代码进⾏验证module clk_div_phase (rst,clk_200K, clk_100K,clk_50K, clk_25K);input clk_200K;input rst;

output clk_100K,clk_50K, clk_25K;wire clk_100K,clk_50K, clk_25K;reg [2:0] cnt;always @ (posedgeclk_200K or negedge rst)if (!rst)cnt <= 3'b000;else

cnt <= cnt + 1;

assign clk_100K = ~cnt [0];assign clk_50K = ~cnt [1];assign clk_25K = ~cnt [2];endmodule测试模块

`timescale 1ns/1psmodule clk_div_phase_tb;reg clk_200K;reg rst;

wire clk_100K, clk_50K, clk_25K;initialbeginrst = 0;clk_200K = 0;# 10;rst = 1;# 3000;$stop;end

clk_div_phase

clk_div_phase_inst (.rst(rst), .clk_200K(clk_200K),.clk_100K(clk_100K),.clk_50K(clk_50K),.clk_25K(clk_25K)

); always # (2500) clk_200K = ~clk_200K;endmodule

2 ⽤代码实现四位⽐较器的设计，并编写测试代码进⾏验证module compare (A, B, AeqB, AgtB, AltB);input [3:0] A, B;

output reg AeqB, AgtB, AltB;always @(A, B)beginAeqB = 0;AgtB = 0;AltB = 0;if(A == B)AeqB = 1;else if (A > B)AgtB = 1;elseAltB = 1;end

endmodule 3 ⽤结构及建模⽅法，描述⼀个4位全加器，并编写测试代码进⾏验证module

add4(a,b,cin,sum,cout);input a,b,cin;output sum,cout;wire s1,m1,m2,m3;and (m1,a,b),xor (s1,a,b),xor (sum,s1,cin);and (m2,s1,cin);or (cout,m1,m2);endmodule

`include \"full_add1.v\"module

add4_1(sum,cout,a,b,cin);

output[3:0] sum;output cout;input[3:0] a,b;input cin;full_add1

f0(a[0],b[0],cin,sum[0],cin1);//级连描述full_add1

f1(a[1],b[1],cin1,sum[1],cin2);full_add1

f2(a[2],b[2],cin2,sum[2],cin3);full_add1

f3(a[3],b[3],cin3,sum[3],cout);

endmodule

4设计⼀个8位补码平⽅器,输⼊是8bit 补码，求其平⽅和。并编写测试代码进⾏验证

说明由于输⼊是补码，所以当最⾼位是l 时，表⽰原值是负数，需要按位取反，加l 后再平⽅;当最⾼位是0时，表⽰原值是正数，直接求平⽅。

module squl(data_in,square);input [7:0] data_in;//输⼊是补码output [15:0] square;wire [7:0] data_bar;

assign data_bar = ~data_in +1;

assign square=(data_in[7])?

(data_bar*data_bar) :(data_in*data_in);endmodule

5 设计⼀个串并转换电路，使串⾏输⼊数据，并⾏4位输出。并编写测试代码验证Module

counter_mod_8(clock,reset,Q);input clock;//posedge effectiveinput reset;output [2:0] Q;reg [2:0] Q;always@(posedge

clock or negedge reset) beginif(~reset)Q <= 3'd0;elseQ <= Q + 1;endendmodule串转并模块：module

ser_to_par_8bit(ser_in,clk,rst,out);

input ser_in,clk,rst;output [7:0] out;wire [7:0] out;reg[7:0] par_out;wire[2:0] count;counter_mod_8

f1(.clock(clk),.reset(rst),.Q(count));

always@(posedge clk or negedge rst) beginif(~rst)

par_out <= 8'b0000_0000;else begin

par_out <= {par_out[6:0],ser_in};endend

assign out = (count == 7)? par_out : 8'b0000_0000;endmodule测试模块

module test_ser_par;reg [7:0] data;wire data_in;reg clock, reset;wire [7:0] out;initial beginclock = 1'b0;reset = 1'b0;#3 reset = 1'b1;data = 8'b1001_1101;#300 $stop;endalways

#5clock = ~clock;always@(posedge clock)data

={data[6:0],data[7]};assign data_in = data[7]ser_to_par_8bit

a(.ser_in(data_in),.clk(clock) ,.rst(reset),.out(out));initial $monitor($time,\"reset= %b,data= %b,data_in= %b,out= %b\endmodule

6 设计⼀个并串转换电

路，是并⾏输⼊数据，串⾏输出，并编写测试代码验证module

para_to_seria(para_in,clock,reset,ser_out);input [7:0] para_in;input reset,clock;output ser_out;wire ser_out;reg ser_out_buf;reg [7:0] data;assign

ser_out=reset?ser_out_buf:1'bz;

always@(posedge clock ornegedge reset) beginif(~reset) beginser_out_buf <= 1'b0;data <= para_in;endelse begindata <=

{data[6:0],data[7]};ser_out_buf <= data[7];endendendmodule测试模块

module test_para_to_ser;reg [7:0] para_in;reg clock,reset;wire out;

para_to_serial_8bit

f1(.para_in(para_in),.clock(clock),.reset(reset),.ser_out(out

));initial

$monitor($time,\"in_8bit= %b,reset= %b,ser_out= %b,data=%b\1.data);initial beginclock = 1'b0;reset = 1'b0;#3 reset = 1'b1;#300 $stop;endinitialpara_in =8'b1010_0100;always

#5clock = ~clock;endmodule