Xilinx ISE Design Suite 10.1 Software Manuals

These software manuals support the Xilinx® Integrated Software Environment (ISE™) software. Click a manual title on the left to view a manual, or click a design step in the following figure to list the manuals associated with that step.

Note:To get started with the software, refer to the “Getting Started Manuals.” For information on graphical user interfaces

(GUIs), see the Help provided with each GUI.

DesignEntryDesign VerificationBehavioralSimulationDesignSynthesisFunctionalSimulationDesignImplementationBackAnnotationStatic TimingAnalysisTimingSimulationXilinx DeviceProgrammingIn-CircuitVerification(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com1

RGetting Started Manuals

Title

ISE Quick Start Tutorial

Summary

•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

•Describes how to get started with the Embedded Development Kit (EDK)•Includes information on the MicroBlaze™ and the IBM® PowerPC® processors

•Includes information on core templates and Xilinx device drivers

EDK Supplemental Information(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com2

RDesign Entry Manuals

Title

ChipScope DocumentationNote:These documents are

available on the Web. ChipScope Pro is one of the Optional Design Tools that can be purchased by clicking Online Store.

Summary

•Explains how to use the ChipScope™ Pro Core Generator™ tool to generate ChipScope Pro cores and add them to an FPGA design

•Explains how to use the ChipScope Pro Core Inserter tool to insert cores into a post-synthesis netlist without disturbing the HDL source code•Explains how to use the ChipScope Pro Analyzer tool to perform in-circuit verification (also known as on-chip debugging), including how to view data and interact with ChipScope Pro cores, how to create bitstreams that are compatible with the ChipScope Pro JTAG download function, and how to download bitstreams to an FPGA using JTAG•Describes each Xilinx constraint, including supported architectures, applicable elements, propagation rules, and syntax examples•Describes constraint types and constraint entry methods•Provides strategies for using timing constraints•Describes supported third party constraints

•Describes how the Data2MEM software tool automates and simplifies setting the contents of BRAM cells on Virtex™ devices.

•Includes how this is used with the 32-bit CPU on the single-chip Virtex-II Pro devices•Describes how to get started with the Embedded Development Kit (EDK)•Includes information on the MicroBlaze and the IBM PowerPC processors•Includes information on core templates and Xilinx device drivers•Describes the function and operation of Virtex-II and Virtex-II Pro

devices, including information on the RocketIO™ transceiver and IBM PowerPC processor

•Describes how to achieve maximum density and performance using the special features of the devices

•Includes information on FPGA configuration techniques and printed circuit board (PCB) design considerations•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

•Includes Xilinx Unified Library information arranged by slice count, supported architectures, and functional categories

•Describes each Xilinx design element, including architectures, usage information, syntax examples, and related constraints•Provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs) •Includes design hints for the novice HDL designer, as well as for the experienced designer who is designing FPGA devices for the first time

Constraints Guide

Data2Mem User Guide

EDK Supplemental InformationNote:These documents are

available on the Web.

Hardware User GuidesNote:These manuals are available

on the Web.

ISE Quick Start Tutorial

Libraries Guide Manuals

Synthesis and Simulation Design Guide

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com3

RTitle

Xilinx/Cadence PCB Guide

Summary

•Provides information information for FPGA designers and Printed Circuit Board (PCB )engineers.

•Includes informaiton about processes and mechanisms available within ISE and various Cadence tools to efficiently implement an FPGA on a PCB.•Provides information information for FPGA designers and Printed Circuit Board (PCB )engineers.

•Includes informaiton about processes and mechanisms available within ISE and various Mentor Graphics tools to efficiently implement an FPGA on a PCB.

Xilinx/Mentor Graphics PCB Guide

Note:For more information, see the ISE Help provided with the Project Navigator GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com4

RDesign Synthesis Manuals

Title

ISE Quick Start Tutorial

Summary

•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

•Provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs) •Includes design hints for the novice HDL designer, as well as for the experienced designer who is designing FPGA devices for the first time•Explains how to use Xilinx Synthesis Technology (XST) synthesis tool, and how it supports HDL languages, Xilinx devices, and constraints•Explains FPGA and CPLD optimization techniques

•Describes how to run XST from the Project Navigator Process window and command line

Synthesis and Simulation Design Guide

XST User Guide

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com5

RDesign Implementation Manuals

Title

Development System Reference Guide

Summary

•Describes Xilinx design flows, including hierarchical design flows such as Incremental Design and Modular Design

•Describes FPGA and CPLD command line tools, including syntax, options, input files, and output filesNote:For information on design implementation, see the “NGDBuild,” “MAP,” “PAR,”

and “BitGen” chapters for FPGAs, and see the “NGDBuild,” “CPLDFit,” and “HPrep6” chapters for CPLDs.

Note:For information on GUIs, such as the Project Navigator, Constraints Editor, ECS, Floorplanner, FPGA Editor, iMPACT,

PACE, Timing Analyzer, and XPower, see the Help provided with each tool.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com6

RBehavioral Simulation Manuals

Title

ISE Quick Start Tutorial

Summary

•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

•Includes Xilinx Unified Library information arranged by slice count, supported architectures, and functional categories

•Describes each Xilinx design element, including architectures, usage information, syntax examples, and related constraints•Provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs) •Includes design hints for the novice HDL designer, as well as for the experienced designer who is designing FPGA devices for the first time

Libraries Guide Manuals

Synthesis and Simulation Design Guide

Note:For more information, see the ISE Help available from the Project Navigator GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com7

RFunctional Simulation Manuals

Title

ISE Quick Start Tutorial

Summary

•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

•Includes Xilinx Unified Library information arranged by slice count, supported architectures, and functional categories

•Describes each Xilinx design element, including architectures, usage information, syntax examples, and related constraints•Provides a general overview of designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs) •Includes design hints for the novice HDL designer, as well as for the experienced designer who is designing FPGA devices for the first time

Libraries Guide Manuals

Synthesis and Simulation Design Guide

Note:For more information, see the ISE Help available from the Project Navigator GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com8

RStatic Timing Analysis Manuals

Title

Development System Reference Guide

Summary

•Describes Xilinx design flows, including hierarchical design flows such as Incremental Design and Modular Design

•Describes FPGA and CPLD command line tools, including syntax, options, input files, and output filesNote:For information on static timing analysis, see the “TRACE” chapter for

FPGAs, and see the “TAEngine” chapter for CPLDs. Also, see the “NetGen” chapter.

Note:For more information, see the Help provided with the Timing Analyzer GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com9

RTiming Simulation and Back Annotation Manuals

Title

Development System Reference Guide

Summary

•Describes Xilinx design flows, including hierarchical design flows such as Incremental Design and Modular Design

•Describes FPGA and CPLD command line tools, including syntax, options, input files, and output filesNote:See the “NetGen” chapter for information on timing simulation and back

annotation.

ISE Quick Start Tutorial

•Explains how to use VHDL and verilog design entry tools•Explains how to perform functional and timing simulation•Explains how to implement a sample design

Note:For more information, see the ISE Help provided with the Project Navigator GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com10

RIn-Circuit Verification Manuals

Title

ChipScope DocumentationNote:These documents are

available on the Web. ChipScope Pro is one of the Optional Design Tools that can be purchased by clicking Online Store.

Summary

•Explains how to use the ChipScope Pro Core Generator tool to generate ChipScope Pro cores and add them to an FPGA design

•Explains how to use the ChipScope Pro Core Inserter tool to insert cores into a post-synthesis netlist without disturbing the HDL source code•Explains how to use the ChipScope Pro Analyzer tool to perform in-circuit verification (also known as on-chip debugging), including how to view data and interact with ChipScope Pro cores, how to create bitstreams that are compatible with the ChipScope Pro JTAG download function, and how to download bitstreams to an FPGA using JTAG•Describes Xilinx implementation tools and design flows, including the hierarchical flows such as Incremental Design, Modular Design, and Partial Reconfiguration

•Includes reference information for Xilinx FPGA and CPLD command line tools, including syntax, input files, output files, and options Note:See the “Design Flow” chapter for information on using “PROBE” in FPGA

Editor.

Development System Reference Guide

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com11

RXilinx Device Programming Manuals

Title

Data SheetsNote:These documents are

available on the Web.

Summary

•Describes the Xilinx device families•Provides device ordering information

•Includes detailed functional descriptions, electrical and performance characteristics, and pinout and package information•Describes the function and operation of Virtex-II and Virtex-II Pro devices, including information on the RocketIO transceiver and IBM PowerPC processor

•Describes how to achieve maximum density and performance using the special features of the devices

•Includes information on FPGA configuration techniques and printed circuit board (PCB) design considerations

Hardware User GuidesNote:These documents are

available on the Web.

Note:For more information, see the Online Help provided with the iMPACT GUI.

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com12

Libraries Guide ManualsRLibraries Guide Manuals

Title

CPLD Libraries Guide

Summary

•Includes Xilinx Unified Library information for CPLD specific devices. •Describes each Xilinx design element, including supported CPLD architectures, usage information, syntax examples, and related constraints•Includes a general description of the Spartan™-II and Spartan-IIE architecture

•Includes a list of all Spartan-II/IIE design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Spartan-II and Spartan-IIE architecture

•Includes a list of all of the Spartan-II/IIE design elements for which

schematic symbols are available, organized by their respective functional categories•Includes a general description of the Spartan-3 architecture

•Includes a list of all Spartan-3 design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Spartan-3 architecture

•Includes a list of all of the Spartan-3 design elements for which schematic symbols are available, organized by their respective functional categories•Includes a general description of the Spartan-3A architecture

•Includes a list of all Spartan-3A design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Spartan-3A architecture•Includes a list of all of the Spartan-3A design elements for which

schematic symbols are available, organized by their respective functional categories•Includes a general description of the Spartan-3E architecture

•Includes a list of all Spartan-3E design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor

Spartan-II and Spartan-IIE

Libraries Guide for HDL Designs

Spartan-II and Spartan-IIE Libraries Guide for Schematic Designs

Spartan-3 Libraries Guide for HDL Designs

Spartan-3 Libraries Guide for Schematic Designs

Spartan-3A and Spartan-3A DSP Libraries Guide for HDL Designs

Spartan-3A and Spartan-3A DSP Libraries Guide for Schematic Designs

Spartan-3E Libraries Guide for HDL Designs

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com13

RTitle

Spartan-3E Libraries Guide for Schematic Designs

Summary

•Includes a general description of the Spartan-3E architecture•Includes a list of all of the Spartan-3E design elements for which

schematic symbols are available, organized by their respective functional categories•Includes a general description of the Virtex and Virtex-E architectures•Includes a list of all Virtex and Virtex-E design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Virtex and Virtex-E architectures•Includes a list of all of the Virtex and Virtex-E design elements for which schematic symbols are available, organized by their respective functional categories•Includes a general description of the Virtex-II architectures

•Includes a list of all Virtex-II design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Virtex-II architectures

•Includes a list of all of the Virtex-II design elements for which schematic symbols are available, organized by their respective functional categories•Includes a general description of the Virtex-II Pro architectures

•Includes a list of all Virtex-II Pro design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Virtex-II Pro architectures•Includes a list of all of the Virtex-II Pro design elements for which

schematic symbols are available, organized by their respective functional categories•Includes a general description of the Virtex-4 LX/SX/FX architectures•Includes a list of all Virtex-4 design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Virtex-4 LX/SX/FX architectures•Includes a list of all of the Virtex-4 design elements for which schematic symbols are available, organized by their respective functional categories

Virtex and Virtex-E Libraries Guide for HDL Designs

Virtex and Virtex-E Libraries Guide for Schematic Designs

Virtex-II Libraries Guide for HDL Designs

Virtex-II Libraries Guide for Schematic Designs

Virtex-II Pro Libraries Guide for HDL Designs

Virtex-II Pro Libraries Guide for Schematic Designs

Virtex-4 Libraries Guide for HDL Designs

Virtex-4 Libraries Guide for Schematic Designs

14www.xilinx.com(c) 2008 Xilinx, Inc. All Rights Reserved

Libraries Guide ManualsRTitle

Virtex-5 Libraries Guide for HDL Designs

Summary

•Includes a general description of the Virtex-5 architectures

•Includes a list of all Virtex-5 design elements that can be instantiated using VHDL or Verilog code organized by functional categories

•Includes examples of code that can be cut and pasted into a design using a text editor•Includes a general description of the Virtex-5 architectures

•Includes a list of all of the Virtex-5 design elements for which schematic symbols are available, organized by their respective functional categories

Virtex-5 Libraries Guide for Schematic Designs

(c) 2008 Xilinx, Inc. All Rights Reservedwww.xilinx.com15