=001:Low-passfilter(-3dBfrequencyatFs/8)Band-passfilter(centerfrequencyat3Fs/16)Band-passfilter(centerfrequencyat5Fs/16)High-passfilter(-3dBfrequencyat3Fs/8)Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comPINCONFIGURATION(CMOSMODE)
RGCPACKAGE(TOPVIEW)CLKOUTDRGNDDRGNDDA10DA11DB1DRVDDDB2DB3DB4DB5DB6DB7DB8DB9DB10DB11RESETSCLKSDATASENAVDD6362616059585756555453525150491482345671011121314154745444342NCDA6DB0DA7DA8DA9NCNCDRGNDDRVDDDRVDDDA5DA4DA3DA2DA1DA0NCNCDRGNDDRVDDCTRL3CTRL2CTRL1AVDDAVDDPAD(ConnectedtoDRGND)4140393837363534163317181920212223242526272829303132VCMINP_BINM_BAGNDAGNDCLKMAGNDAGNDAGNDAGNDAGNDAGNDINP_AINM_AAGNDCLKPP0056-11PinAssignments(CMOSINTERFACE)
PINNAMEAVDDAGNDCLKP,CLKMINP_A,INM_AINP_B,INM_BVCM
AnalogpowersupplyAnaloggroundDifferentialinputclock
Differentialinputsignal–channelADifferentialinputsignal–channelB
Internalreferencemode–Common-modevoltageoutput.
Externalreferencemode–Referenceinput.ThevoltageforcedonthispinsetstheADCinternalreferences.
SerialinterfaceRESETinput.
Inserialinterfacemode,theusermustinitializeinternalregistersthroughhardwareRESETbyapplyingahigh-goingpulseonthispinorbyusingsoftwarereset(refertoSerialInterfacesection).
Inparallelinterfacemode,theuserhastotieRESETpinpermanentlyhigh.(SCLK,SDATAandSENareusedasparallelpincontrolsinthismode)Thepinhasaninternal100kΩpull-downresistor.
DESCRIPTION
PINNUMBER16,33,3417,18,21,22,24,27,28,31,32
25,2629,3019,2023
NUMBEROF
PINS
392221
RESET121
22SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
PinAssignments(CMOSINTERFACE)(continued)
PINNAMESCLKDESCRIPTIONThispinfunctionsasserialinterfaceclockinputwhenRESETislow.ItfunctionsasanalogcontrolpinwhenRESETistiedhighandcontrolscoarsegainandinternal/externalreferenceselection.SeeTable2fordetails.Thepinhasaninternalpull-downresistortoground.ThispinfunctionsasserialinterfacedatainputwhenRESETislow.Thepinhasaninternalpull-downresistortoground.ThispinfunctionsasserialinterfaceenableinputwhenRESETislow.ItfunctionsasanalogcontrolpinwhenRESETistiedhighandcontrolstheoutputinterface(LVDS/CMOS)anddataformatselection.SeeTable3fordetails.Thepinhasaninternalpull-upresistortoAVDD.Thesearedigitallogicinputpins.Togethertheycontrolvariouspowerdownandmultiplexedmode.seeTable4fordetailsPINNUMBER13NUMBEROFPINS1SDATASEN141511CTRL1CTRL2CTRL3DA11toDA0DB11toDB0CLKOUTDRVDDDRGNDPADNC35363742-47,50-5562-63,2-11571,38,48,5839,49,59,andPAD–40,41,60,61,56111121214415ChannelA12-bitdataoutputs,CMOSChannelB12-bitdataoutputs,CMOSCMOSoutputclockDigitalsupplyDigitalgroundDigitalground.Solderthepadtothedigitalgroundontheboardusingmultipleviasforgoodelectricalandthermalperformance.DonotconnectCopyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comPINCONFIGURATION(LVDSMODE)
RGCPACKAGE(TOPVIEW)CLKOUTPCLKOURGNDDRGNDDRVDDDA10PDRVDDDB2MDB2PDB4MDB4PDB6MDB6PDB8MDB8PDB10MDB10PRESETSCLKSDATASENAVDD6362616059585756555453525150491482345671011121314154745444342DA6MDB0MDB0PDA6PDA8PNCNCDRGNDDA10MDA8MDRVDDDA4PDA4MDA2PDA2MDA0PDA0MNCNCDRGNDDRVDDCTRL3CTRL2CTRL1AVDDAVDDPAD(ConnectedtoDRGND)4140393837363534163317181920212223242526272829303132VCMINM_BINP_BCLKMAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDINP_AINM_AAGNDCLKPP0056-12PinAssignments(LVDSINTERFACE)
PINNAMEAVDDAGND
AnalogpowersupplyAnalogground
DESCRIPTION
PINNUMBER16,33,3417,18,21,22,24,27,28,31,3225,2629,3019,2023
NUMBEROF
PINS
39
CLKP,CLKMINP_A,INM_AINP_B,INM_BVCM
Differentialinputclock
Differentialinputsignal–ChannelADifferentialinputsignal–ChannelB
Internalreferencemode–Common-modevoltageoutput.
Externalreferencemode–Referenceinput.ThevoltageforcedonthispinsetstheADCinternalreferences.
SerialinterfaceRESETinput.
Inserialinterfacemode,theusermustinitializeinternalregistersthroughhardwareRESETbyapplyingahigh-goingpulseonthispinorbyusingsoftwarereset(refertoSerialInterfacesection).
Inparallelinterfacemode,theuserhastotieRESETpinpermanentlyhigh.(SCLK,SDATAandSENareusedasparallelpincontrolsinthismode)Thepinhasaninternal100kΩpull-downresistor.
2221
RESET121
24SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
PinAssignments(LVDSINTERFACE)(continued)
PINNAMESCLKDESCRIPTIONThispinfunctionsasserialinterfaceclockinputwhenRESETislow.ItfunctionsasanalogcontrolpinwhenRESETistiedhighandcontrolscoarsegainandinternal/externalreferenceselection.SeeTable2fordetails.Thepinhasaninternalpull-downresistortoground.ThispinfunctionsasserialinterfacedatainputwhenRESETislow.Thepinhasaninternalpull-downresistortoground.ThispinfunctionsasserialinterfaceenableinputwhenRESETislow.ItfunctionsasanalogcontrolpinwhenRESETistiedhighandcontrolstheoutputinterface(LVDS/CMOS)anddataformatselection.SeeTable3fordetails.Thepinhasaninternalpull-upresistortoAVDD.Thesearedigitallogicinputpins.Togethertheycontrolvariouspowerdownandmultiplexedmode.SeeTable4fordetails.PINNUMBER13NUMBEROFPINS1SDATASEN141511CTRL1CTRL2CTRL3DA0PDA0MDA2PDA2MDA4PDA4MDA6PDA6MDA8PDA8MDA10PDA10MCLKOUTPCLKOUB0PDB0MDB2PDB2MDB4PDB4MDB6PDB6MDB8PDB8MDB10PDB10MDRVDDDRGNDPADNC353637434245444746515053525554575663623254769811101,38,48,5839,49,59,andPAD–40,41,60,61111111111111111111111111111114414ChannelADifferentialoutputdataD0andD1multiplexed,trueChannelADifferentialoutputdataD0andD1multiplexed,complementChannelADifferentialoutputdataD2andD3multiplexed,trueChannelADifferentialoutputdataD2andD3multiplexed,complementChannelADifferentialoutputdataD4andD5multiplexed,trueChannelADifferentialoutputdataD4andD5multiplexed,complementChannelADifferentialoutputdataD6andD7multiplexed,trueChannelADifferentialoutputdataD6andD7multiplexed,complementChannelADifferentialoutputdataD8andD9multiplexed,trueChannelADifferentialoutputdataD8andD9multiplexed,complementChannelADifferentialoutputdataD10andD11multiplexed,trueChannelADifferentialoutputdataD10andD11multiplexed,complementDifferentialoutputclock,trueDifferentialoutputclock,complementChannelBDifferentialoutputdataD0andD1multiplexed,trueChannelBDifferentialoutputdataD0andD1multiplexed,complementChannelBDifferentialoutputdataD2andD3multiplexed,trueChannelBDifferentialoutputdataD2andD3multiplexed,complementChannelBDifferentialoutputdataD4andD5multiplexed,trueChannelBDifferentialoutputdataD4andD5multiplexed,complementChannelBDifferentialoutputdataD6andD7multiplexed,trueChannelBDifferentialoutputdataD6andD7multiplexed,complementChannelBDifferentialoutputdataD8andD9multiplexed,trueChannelBDifferentialoutputdataD8andD9multiplexed,complementChannelBDifferentialoutputdataD10andD11multiplexed,trueChannelBDifferentialoutputdataD10andD11multiplexed,complementDigitalsupplyDigitalgroundDigitalground.Solderthepadtothedigitalgroundontheboardusingmultipleviasforgoodelectricalandthermalperformance.DonotconnectCopyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P25(FS=125MSPS)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutput
interface(unlessotherwisenoted)
FFTfor20MHzINPUTSIGNAL
0−20−40SFDR = 88.31 dBcSINAD = 70.95 dBFSSNR = 71.03 dBFSTHD = 87.1 dBcFFTfor70MHzINPUTSIGNAL
0−20−40SFDR = 86.51 dBcSINAD = 70.88 dBFSSNR = 71.01 dBFSTHD = 85.12 dBcAmplitude − dB−60−80−100−120−140−1600102030405060G001Amplitude − dB−60−80−100−120−140−1600102030405060G002f − Frequency − MHzf − Frequency − MHzFigure7.
FFTfor190MHzINPUTSIGNAL
0−20−40SFDR = 78.88 dBcSINAD = 69.49 dBFSSNR = 70.11 dBFSTHD = 77.27 dBcFigure8.
INTERMODULATIONDISTORTION(IMD)vsFREQUENCY
0−20−40fIN1 = 190.1 MHz, –7 dBFSfIN2 = 185.3 MHz, –7 dBFS2-Tone IMD = –88.5 dBFSSFDR = –96.08 dBFSAmplitude − dB−60−80−100−120−140−1600102030405060G003Amplitude − dB−60−80−100−120−140−1600102030405060G004f − Frequency − MHzf − Frequency − MHzFigure9.
SFDRvsINPUTFREQUENCY
949290Gain = 3.5 dB747372Figure10.
SNRvsINPUTFREQUENCY
SNR − dBFSSFDR − dBc888684828078760255075100125150175200G005Gain = 0 dB7170696867660255075100125150175200G006Gain = 3.5 dBGain = 0 dBfIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure11.Figure12.
26SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P25(FS=125MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
SFDRvsINPUTFREQUENCY(LVDSinterface)
949290Gain = 3.5 dB9492904 dBInput adjusted to get −1dBFS input2 dB3 dBSFDRvsINPUTFREQUENCYACROSSGAIN
SFDR − dBc8684828078760255075100125150175200G007SFDR − dBc88888684828078760255075100125150175200G0095 dB6 dB1 dB0 dBGain = 0 dBfIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure13.
SINADvsINPUTFREQUENCYACROSSGAIN
7372710 dBInput adjusted to get −1dBFS input1 dB2 dBSFDR − dBcFigure14.
PERFORMANCEvsAVDD
90883 dB76fIN = 70.1 MHzDRVDD = 3.3 V75SFDR7473SNR727170693.13.23.33.43.5683.6G011SINAD − dBFS87868584696867666502040604 dB5 dB6 dB80100120140160180200G01083823.0fIN − Input Frequency − MHzAVDD − Supply Voltage − VFigure15.
PERFORMANCEvsDRVDD
9088SFDR − dBcFigure16.
PERFORMANCEvsTEMPERATURE
76fIN = 70.1 MHz888786SNR858483−40G0127574SFDR7372717069−20020406080G013fIN = 70.1 MHzAVDD = 3.3 VSFDR757486SNR858483823.03.13.23.33.43.572717069683.6DRVDD − Supply Voltage − VT − Temperature − °CFigure17.Figure18.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFSSFDR − dBc8773SNR − dBFSSNR − dBFS7027
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P25(FS=125MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
PERFORMANCEvsINPUTAMPLITUDE
110100SFDR − dBc, dBFSPERFORMANCEvsCLOCKAMPLITUDE
90949290SNR − dBFSSFDR − dBc76fIN = 20.1 MHzSFDR757473SNR727170691.01.52.02.5683.0G015SFDR (dBFS)85807590807060504030−60−50SFDR (dBc)fIN = 20.1 MHz−40−30−20−100SNR (dBFS)8886848280780.57065605550Input Amplitude − dBFSG014Input Clock Amplitude − VPPFigure19.
PERFORMANCEvsINPUTCLOCKDUTYCYCLE
949290SFDR − dBcFigure20.
OUTPUTNOISEHISTOGRAM(INPUTSTIEDTOCOMMON-MODE)
706077fIN = 20.1 MHzSFDR7675Occurence − %SNR − dBFS8886848280787630354045747350403020100204020412042204320442045204620472048Output CodeG017SNR72717069685055606570G016Input Clock Duty Cycle − %Figure21.
PERFORMANCEINEXTERNALREFERENCEMODE
9391SFDR − dBcFigure22.
78SFDR76SNR − dBFSfIN = 20.1 MHzExternal Reference Mode7487SNR7285831.3570681.65G0181.401.451.501.551.60VVCM − VCM Voltage − VFigure23.
28SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFS元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P24(FS=105MSPS)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutput
interface(unlessotherwisenoted)
FFTfor20MHzINPUTSIGNAL
0−20−40SFDR = 88.38 dBcSINAD = 71.02 dBFSSNR = 71.09 dBFSTHD = 87.61 dBcFFTfor70MHzINPUTSIGNAL
0−20−40SFDR = 84.17 dBcSINAD = 70.8 dBFSSNR = 71.01 dBFSTHD = 83 dBcAmplitude − dB−60−80−100−120−140−16001020304050G019Amplitude − dB−60−80−100−120−140−16001020304050G020f − Frequency − MHzf − Frequency − MHzFigure24.
FFTfor190MHzINPUTSIGNAL
0−20−40SFDR = 82.51 dBcSINAD = 69.71 dBFSSNR = 70.04 dBFSTHD = 80.13 dBcFigure25.
INTERMODULATIONDISTORTION(IMD)vsFREQUENCY
0−20−40fIN1 = 190.1 MHz, –7 dBFSfIN2 = 185.3 MHz, –7 dBFS2-Tone IMD = –87 dBFSSFDR = –90 dBFSAmplitude − dB−60−80−100−120−140−16001020304050G021Amplitude − dB−60−80−100−120−140−16001020304050G022f − Frequency − MHzf − Frequency − MHzFigure26.
SFDRvsINPUTFREQUENCY
969492Gain = 3.5 dB7473Figure27.
SNRvsINPUTFREQUENCY
SFDR − dBc90888684828078760255075100125150175200G023SNR − dBFS727170Gain = 0 dBGain = 3.5 dBGain = 0 dB69680255075100125150175200G024fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure28.Figure29.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P24(FS=105MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
SFDRvsINPUTFREQUENCY(LVDSinterface)
969492Gain = 3.5 dB9694925 dBInput adjusted to get −1dBFS input2 dB3 dBSFDRvsINPUTFREQUENCYACROSSGAIN
SFDR − dBc8886848280780255075100125150175200G025SFDR − dBc90908886848280780255075100125150175200G027Gain = 0 dB4 dB6 dB0 dB1 dBfIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure30.
SINADvsINPUTFREQUENCYACROSSGAIN
7372710 dBInput adjusted to get −1dBFS input1 dB2 dB3 dBSFDR − dBcFigure31.
PERFORMANCEvsAVDD
88878685848382SNRfIN = 70.1 MHzDRVDD = 3.31 V7675SFDR7473727170693.13.23.33.43.5683.6G029SINAD − dBFS7069686766650255075100125150175200G0284 dB5 dB6 dB81803.0fIN − Input Frequency − MHzAVDD − Supply Voltage − VFigure32.
PERFORMANCEvsDRVDD
9088SFDR − dBcFigure33.
PERFORMANCEvsTEMPERATURE
7788SNR − dBFS757473SFDR72SNR7170fIN = 70.1 MHz69−20020406080G031fIN = 70.1 MHzAVDD = 3.31 V7675SFDR86858483823.03.13.23.33.43.5SNR73727170693.686858483−40DRVDD − Supply Voltage − VG030T − Temperature − °CFigure34.Figure35.
30SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFSSFDR − dBc877487SNR − dBFS元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P24(FS=105MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
PERFORMANCEvsINPUTAMPLITUDE
110SFDR (dBFS)100SFDR − dBc, dBFSPERFORMANCEvsCLOCKAMPLITUDE
908580SFDR − dBc949290SNR − dBFS77fIN = 20.1 MHz76757473SNR7271700.51.01.52.02.5693.0G03390807060504030−60fIN = 20.1 MHz−50−40−30−20−100SFDR (dBc)SNR (dBFS)7570656055508886848280780.0Input Amplitude − dBFSG032Input Clock Amplitude − VPPFigure36.
PERFORMANCEvsINPUTCLOCKDUTYCYCLE
949290SFDR − dBcFigure37.
OUTPUTNOISEHISTOGRAMWITHINPUTSTIEDTOCOMMON-MODE
605079fIN = 20.1 MHzSFDR7877868482807876303540455055606570Input Clock Duty Cycle − %SNR757473727170Occurence − %SNR − dBFS88703020100204020412042204320442045204620472048Output CodeG035G034Figure38.
PERFORMANCEINEXTERNALREFERENCEMODE
9593SFDRSFDR − dBcFigure39.
7977SNR − dBFSfIN = 20.1 MHzExternal Reference Mode9175SNR87851.357371691.65G0361.401.451.501.551.60VVCM − VCM Voltage − VFigure40.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFSSFDR31
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P23(FS=80MSPS)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutput
interface(unlessotherwisenoted)
FFTfor20MHzINPUTSIGNAL
0−20−40SFDR = .61 dBcSINAD = 71.22 dBFSSNR = 71.44 dBFSTHD = 83.3 dBcFFTfor70MHzINPUTSIGNAL
0−20−40SFDR = 90.05 dBcSINAD = 71.19 dBFSSNR = 71.25 dBFSTHD = .09 dBcAmplitude − dB−60−80−100−120−140−16001020f − Frequency − MHz3040G037Amplitude − dB−60−80−100−120−140−16001020f − Frequency − MHz3040G038Figure41.
FFTfor190MHzINPUTSIGNAL
0−20−40SFDR = 84.12 dBcSINAD = 70.22 dBFSSNR = 70.45 dBFSTHD = 82.11 dBcFigure42.
INTERMODULATIONDISTORTION(IMD)vsFREQUENCY
0−20−40fIN1 = 190.1 MHz, –7 dBFSfIN2 = 185.3 MHz, –7 dBFS2-Tone IMD = –93 dBFSSFDR = –98 dBFSAmplitude − dB−60−80−100−120−140−16001020f − Frequency − MHz3040G039Amplitude − dB−60−80−100−120−140−16001020f − Frequency − MHz3040G040Figure43.
SFDRvsINPUTFREQUENCY
9694Gain = 3.5 dB7473Figure44.
SNRvsINPUTFREQUENCY
SNR − dBFSSFDR − dBc929088868482800255075100125150175200G041727170696802550Gain = 0 dBGain = 0 dBGain = 3.5 dB75100125150175200G042fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure45.Figure46.
32SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P23(FS=80MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
SFDRvsINPUTFREQUENCY(LVDSinterface)
9694Gain = 3.5 dB9694Input adjusted to get −1dBFS input4 dB3 dB5 dBSFDRvsINPUTFREQUENCYACROSSGAIN
SFDR − dBc9088868482800255075100125150175200G043SFDR − dBc929290888684828002550756 dBGain = 0 dB1 dB0 dB1002 dB125150175200G045fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure47.
SINADvsINPUTFREQUENCYACROSSGAIN
747372Input adjusted to get −1dBFS input0 dB1 dB2 dBSFDR − dBcFigure48.
PERFORMANCEvsAVDD
9694923 dB77fIN = 70.1 MHzDRVDD = 3.31 VSFDR76757473SNR7271703.13.23.33.43.5693.6G047SINAD − dBFS908886847069686766650255075100125150175200G04 dB5 dB6 dB82803.0fIN − Input Frequency − MHzAVDD − Supply Voltage − VFigure49.
PERFORMANCEvsDRVDD
969492SFDR − dBcFigure50.
PERFORMANCEvsTEMPERATURE
7792908886848280−40G04876SFDRfIN = 70.1 MHz757473727170−20020406080G049fIN = 70.1 MHzAVDD = 3.31 V7675SFDR − dBcSFDR88868482803.03.13.23.33.43.5SNR73727170693.6SNRDRVDD − Supply Voltage − VT − Temperature − °CFigure51.Figure52.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFS9074SNR − dBFSSNR − dBFS7133
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P23(FS=80MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
PERFORMANCEvsINPUTAMPLITUDE
110100SFDR − dBc, dBFSPERFORMANCEvsCLOCKAMPLITUDE
90949290SNR − dBFS77fIN = 20.1 MHz76757473SNR7271700.51.01.52.02.5693.0G051SFDR (dBFS)858090807060504030−60fIN = 20.1 MHz−50−40−30−20−100SFDR (dBc)SNR (dBFS)7065605550SFDR − dBc758886848280780.0Input Amplitude − dBFSG050Input Clock Amplitude − VPPFigure53.
PERFORMANCEvsINPUTCLOCKDUTYCYCLE
969492SFDR − dBcFigure54.
OUTPUTNOISEHISTOGRAMWITHINPUTSTIEDTOCOMMON-MODE
90807078fIN = 20.1 MHz77768886848280782530354045505560657075Input Clock Duty Cycle − %SNR747372717069Occurence − %SNR − dBFS90SFDR756050403020100204020412042204320442045204620472048Output CodeG053G052Figure55.
PERFORMANCEINEXTERNALREFERENCEMODE
9290SFDR − dBcFigure56.
8078SFDRSNR − dBFSfIN = 20.1 MHzExternal Reference Mode8876867484821.35SNR72701.65G0541.401.451.501.551.60VVCM − VCM Voltage − VFigure57.
34SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFSSFDR元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P22(FS=65MSPS)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutput
interface(unlessotherwisenoted)
FFTfor20MHzINPUTSIGNAL
0−20−40SFDR = 87.17 dBcSINAD = 71.33 dBFSSNR = 71.43 dBFSTHD = 86.73 dBcFFTfor70MHzINPUTSIGNAL
0−20−40SFDR = 87.71 dBcSINAD = 71.21 dBFSSNR = 71.29 dBFSTHD = 87.42 dBcAmplitude − dB−60−80−100−120−140−1600102030G055Amplitude − dB−60−80−100−120−140−1600102030G056f − Frequency − MHzf − Frequency − MHzFigure58.
FFTfor190MHzINPUTSIGNAL
0−20−40SFDR = 81.79 dBcSINAD = 69. dBFSSNR = 69. dBFSTHD = 81.28 dBcFigure59.
INTERMODULATIONDISTORTION(IMD)vsFREQUENCY
0−20−40fIN1 = 190.1 MHz, –7 dBFSfIN2 = 185.3 MHz, –7 dBFS2-Tone IMD = –92 dBFSSFDR = –94.5 dBFSAmplitude − dB−60−80−100−120−140−1600102030G057Amplitude − dB−60−80−100−120−140−1600102030G058f − Frequency − MHzf − Frequency − MHzFigure60.
SFDRvsINPUTFREQUENCY
9694Gain = 3.5 dB7473Figure61.
SNRvsINPUTFREQUENCY
SNR − dBFSSFDR − dBc929088868482800255075100125150175200G059727170696802550Gain = 0 dBGain = 3.5 dBGain = 0 dB75100125150175200G060fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure62.Figure63.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback35
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-ADS62P22(FS=65MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
SFDRvsINPUTFREQUENCY(LVDSinterface)
96949694Input adjusted to get −1dBFS input4 dB3 dBSFDRvsINPUTFREQUENCYACROSSGAIN
SFDR − dBc9088868482800255075100125150175200G061SFDR − dBc92Gain = 3.5 dB92908886848280025506 dB0 dB1 dB751005 dBGain = 0 dB2 dB125150175200G063fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure.
SINADvsINPUTFREQUENCYACROSSGAIN
73720 dBInput adjusted to get −1dBFS input1 dB2 dBSFDR − dBcFigure65.
PERFORMANCEvsAVDD
969492fIN = 70.1 MHzDRVDD = 3.31 VSFDR90888684SNR74737271703.13.23.33.43.5693.6G065777675SNR − dBFSG067SINAD − dBFS71706968676602550751004 dB5 dB3 dB6 dB125150175200G082803.0fIN − Input Frequency − MHzAVDD − Supply Voltage − VFigure66.
PERFORMANCEvsDRVDD
939291SFDR − dBcFigure67.
PERFORMANCEvsTEMPERATURE
7792fIN = 70.1 MHz91SNR − dBFS76SFDR757473727170−20020406080T − Temperature − °CfIN = 70.1 MHzAVDD = 3.31 VSFDR7675888786853.03.13.23.33.43.5SNR73727170693.6888786−40SNRDRVDD − Supply Voltage − VG066Figure68.Figure69.
36SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFSSFDR − dBc907490元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
TYPICALCHARACTERISTICS-ADS62P22(FS=65MSPS)(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
PERFORMANCEvsINPUTAMPLITUDE
110100SFDR − dBc, dBFSPERFORMANCEvsCLOCKAMPLITUDE
90949290SNR − dBFSSFDR − dBc7675SFDR7473SNR72717069fIN = 20.1 MHz0.51.01.52.02.5683.0G069SFDR (dBFS)858090807060504030−60fIN = 20.1 MHz−50−40−30−20−100SFDR (dBc)SNR (dBFS)7570656055508886848280780.0Input Amplitude − dBFSG068Input Clock Amplitude − VPPFigure70.
PERFORMANCEvsINPUTCLOCKDUTYCYCLE
10096SFDR − dBcFigure71.
OUTPUTNOISEHISTOGRAMWITHINPUTSTIEDTOCOMMON-MODE
80706078fIN = 20.1 MHzSFDR7776Occurence − %SNR − dBFS949290888684822530354045505560657075Input Clock Duty Cycle − %SNR75747372717069504030201002040204120422043204420452046204720482049Output CodeG071G070Figure72.
PERFORMANCEINEXTERNALREFERENCEMODE
9593SFDR9176SFDR − dBcFigure73.
8078SNR − dBFSfIN = 20.1 MHzExternal Reference ModeSNR7487851.3572701.65G0721.401.451.501.551.60VVCM − VCM Voltage − VFigure74.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
SNR − dBFS37
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTYPICALCHARACTERISTICS-LOWSAMPLINGFREQUENCIES
Allplotsareat25°C,AVDD=DRVDD=3.3V,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
FS=25MSPS
SFDRvsINPUTFREQUENCY
1101007876Gain = 3.5 dB908074SNRvsINPUTFREQUENCY
SNR − dBFSSFDR − dBc727068Gain = 0 dBGain = 0 dBGain = 3.5 dB70600255075100125150175200G075660255075100125150175200G076fIN − Input Frequency − MHzfIN − Input Frequency − MHzFigure75.Figure76.
COMMONPLOTS
Allplotsareat25°C,AVDD=DRVDD=3.3V,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
POWERDISSIPATIONvs
SAMPLINGFREQUENCY(DDRLVDSandCMOS)
0.80.70.60.50.40.30.20.10.0050100150200250300G077COMMON-MODEREJECTIONRATIOvsFREQUENCY
0−10−20−30−40−50−60−70−80−90−100f − Frequency − MHzPD − Power Dissipation − WfIN = 2.5 MHzCL = 5 pFCMRR − dBcLVDSCMOS0255075100125G078fS − Sampling Frequency − MSPSFigure77.Figure78.
38SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
COMMONPLOTS(continued)
Allplotsareat25°C,AVDD=DRVDD=3.3V,sinewaveinputclock,1.5VPPdifferentialclockamplitude,50%clockdutycycle,–1dBFSdifferentialanaloginput,internalreferencemode,0dBgain,CMOSoutputinterface(unlessotherwisenoted)
DRVDDcurrent(CMOSinterface)vs
SAMPLINGFREQUENCYacrossloadcapacitance
301.8 V, No Load25DRVDD Current − mA1.8 V, 5 pF3.3 V, No Load3.3 V, 5 pF3.3 V, 10 pF201510500255075100125G079fS − Sampling Frequency − MSPSFigure79.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comAPPLICATIONINFORMATION
THEORYOFOPERATION
ADS62P2Xisalowpower12-bitdualchannelpipelineADCfamilyfabricatedinaCMOSprocessusingswitchedcapacitortechniques.
Theconversionprocessisinitiatedbyarisingedgeoftheexternalinputclock.Oncethesignaliscapturedbytheinputsampleandhold,theinputsampleissequentiallyconvertedbyaseriesofsmallresolutionstages,withtheoutputscombinedinadigitalcorrectionlogicblock.Ateveryclockedgethesamplepropagatesthroughthepipelineresultinginadatalatencyof14clockcycles.Theoutputisavailableas12-bitdata,inDDRLVDSorCMOSandcodedineitherstraightoffsetbinaryorbinary2scomplementformat.
ANALOGINPUT
Theanaloginputconsistsofaswitched-capacitorbaseddifferentialsampleandholdarchitecture.
ThisdifferentialtopologyresultsinverygoodACperformanceevenforhighinputfrequenciesathighsamplingrates.TheINPandINMpinshavetobeexternallybiasedaroundacommon-modevoltageof1.5V,availableonVCMpin13.Forafull-scaledifferentialinput,eachinputpinINP,INMhastoswingsymmetricallybetweenVCM+0.5VandVCM–0.5V,resultingina2VPPdifferentialinputswing.ThemaximumswingisdeterminedbytheinternalreferencevoltagesREFP(2.5Vnominal)andREFM(0.5V,nominal).
SamplingSwitchLpkg»2nHINPCbond»1pF25WResr100W50W3.2pFLpkg»2nHINMCbond»1pFResr100WCpar21pFSamplingSwitchS0322-01RCRFilterRon15WSamplingCapacitorCpar21pFCpar10.8pFRon15WCsamp4pFRon10WCsamp4pFSamplingCapacitor50W25WFigure80.AnalogInputEquivalentCircuit
Theinputsamplingcircuithasahigh3-dBbandwidththatextendsupto450MHz(measuredfromtheinputpinstothesampledvoltage).
40SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
10−1Magnitude − dB−2−3−4−5−6−70100200300400500600G080fI − Input Frequency − MHzFigure81.ADCAnalogBandwidth
DriveCircuitRequirements
Foroptimumperformance,theanaloginputsmustbedrivendifferentially.Thisimprovesthecommon-modenoiseimmunityandevenorderharmonicrejection.A<5Ωresistorinserieswitheachinputpinisrecommendedtodampoutringingcausedbythepackageparasitics.
Itisalsonecessarytopresentlowimpedance(50Ω)forthecommonmodeswitchingcurrents.Thiscanbeachievedbyusingtworesistorsfromeachinputterminatedtothecommonmodevoltage(VCM).
Inaddition,thedrivecircuitmayhavetobedesignedtoprovidealowinsertionlossoverthedesiredfrequencyrangeandmatchedimpedancetothesource.Whiledoingthis,theADCinputimpedancemustbeconsidered.Figure82andFigure83showtheimpedance(Zin=Rin||Cin)lookingintotheADCinputpins.
100R − Resistance − kΩ1010.10.010100200300400500600G081f − Frequency − MHzFigure82.ADCAnalogInputResistance(Rin)AcrossFrequency
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.com98C − Capacitance − pF765432100100200300400500600G082f − Frequency − MHzFigure83.ADCAnalogInputCapacitance(Cin)AcrossFrequency
UsingRF-TransformerBasedDriveCircuits
Figure84showsaconfigurationusingasingle1:1turnsratiotransformer(forexample,CoilcraftWBC1-1)thatcanbeusedforlowinputfrequencies(about100MHz).Thesingle-endedsignalisfedtotheprimarywindingoftheRFtransformer.Thetransformeristerminatedonthesecondaryside.PuttingtheterminationonthesecondarysidehelpstoshieldthekickbackscausedbythesamplingcircuitfromtheRFtransformer’sleakageinductances.Theterminationisaccomplishedbytworesistorsconnectedinseries,withthecenterpointconnectedtothe1.5Vcommonmode(VCMpin).Thevalueoftheterminationresistors(connectedtocommonmode)hastobelow(<100Ω)toprovidealow-impedancepathfortheADCcommon-modeswitchingcurrents.
ADS62P2x0.1mFINP0.1mF25W25WINM1:1VCMS0163-04Figure84.DriveCircuitatLowInputFrequencies
Athighinputfrequencies,themismatchinthetransformerparasiticcapacitance(betweenthewindings)resultsindegradedeven-orderharmonicperformance.ConnectingtwoidenticalRFtransformersback-to-backhelpsminimizethismismatch,andgoodperformanceisobtainedforhighfrequencyinputsignals.Figure85showsanexampleusingtwotransformers(CoilcraftWBC1-1).Anadditionalterminationresistorpair(enclosedwithintheshadedbox)mayberequiredbetweenthetwotransformerstoimprovethebalancebetweenthePandMsides.Thecenterpointofthisterminationmustbeconnectedtoground.
42SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
ADS62P2x0.1mF
INP50W0.1mF50W50W50WINM1:1
1:1
VCMS01-07
Figure85.DriveCircuitatHighInputFrequencies
UsingDifferentialAmplifierDriveCircuits
Figure86showsadrivecircuitusingadifferentialamplifier(TI'sTHS4509)toconvertasingle-endedinputtodifferentialoutputthatcanbeinterfacetotheADCanaloginputpins.Inadditiontothesingle-endedtodifferentialconversion,theamplifieralsoprovidesgain(10dB).RFILhelpstoisolatetheamplifieroutputsfromtheswitchinginputoftheADC.TogetherwithCFILitalsoformsalow-passfilterthatband-limitsthenoise(andsignal)attheADCinput.Astheamplifieroutputisac-coupled,thecommon-modevoltageoftheADCinputpinsissetusingtwo200ΩresistorsconnectedtoVCM.
Theamplifieroutputcanalsobedc-coupled.Usingtheoutputcommon-modecontroloftheTHS4509,theADCinputpinscanbebiasedto1.5V.Inthiscase,use+4Vand–1VsuppliesfortheTHS4509sothatitsoutputcommon-modevoltage(1.5V)isatmid-supply.
RF+VS500WRS0.1mFRG0.1mFCMTHS4509RGRFIL500W–VS0.1mF10mF0.1mFCFIL0.1mF200WINMRS||RT0.1mF5WVCMCFIL200W0.1mF10mFRFIL0.1mFADS62P2x5WINPRTRFS0259-04Figure86.DriveCircuitUsingtheTHS4509
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comInputCommon-Mode
Toensurealow-noisecommon-modereference,theVCMpinisfilteredwitha0.1µFlow-inductancecapacitorconnectedtoground.TheVCMpinisdesignedtodirectlydrivetheADCinputs.TheinputstageoftheADCsinksacommon-modecurrentintheorderof165µA(at125MSPS).Equation1describesthedependencyofthecommon-modecurrentandthesamplingfrequency.
165mA Fs125MSPS(1)ThisequationhelpstodesigntheoutputcapabilityandimpedanceoftheCMdrivingcircuitaccordingly.
REFERENCE
ADS62P2Xhasbuilt-ininternalreferencesREFPandREFM,requiringnoexternalcomponents.Designschemes
areusedtolinearizetheconverterloadseenbythereferences;thisandtheon-chipintegrationoftherequisitereferencecapacitorseliminatestheneedforexternaldecoupling.Thefull-scaleinputrangeoftheconvertercanbecontrolledintheexternalreferencemodeasexplainedbelow.Theinternalorexternalreferencemodescanbeselectedbyprogrammingtheserialinterfaceregisterbit(REF).INTREFVCMInternalReference1kW4kWINTREFEXTREFREFMREFPADS62P2xS0165-07Figure87.ReferenceSection
InternalReference
Whenthedeviceisininternalreferencemode,theREFPandREFMvoltagesaregeneratedinternally.Common-modevoltage(1.5Vnominal)isoutputonVCMpin,whichcanbeusedtoexternallybiastheanaloginputpins.
ExternalReference
Whenthedeviceisinexternalreferencemode,theVCMactsasareferenceinputpin.ThevoltageforcedontheVCMpinisbufferedandgainedby1.33internally,generatingtheREFPandREFMvoltages.Thedifferentialinputvoltagecorrespondingtofull-scaleisgiveninEquation2.Full-scaledifferentialinputpp=(VoltageforcedonVCM)×1.33
(2)
44SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
Inthismode,the1.5Vcommon-modevoltagetobiastheinputpinshastobegeneratedexternally.
COARSEGAINANDPROGRAMMABLEFINEGAIN
ADS62P2XincludesgainsettingsthatcanbeusedtogetimprovedSFDRperformance(over0dBgainmode).Foreachgainsetting,theanaloginputfull-scalerangescalesproportionally,asshowninTable18.Thecoarsegainisafixedsettingof3.5dBandisdesignedtoimproveSFDRwithlittledegradationinSNR.Thefinegainisprogrammablein0.5dBstepsfrom0to6dB;howevertheSFDRimprovementisachievedattheexpenseofSNR.So,theprogrammablefinegainmakesitpossibletotrade-offbetweenSFDRandSNR.ThecoarsegainmakesitpossibletogetbestSFDRbutwithoutlosingSNRsignificantly.
Thegainscanbeprogrammedusingtheserialinterface(bitsCOARSEGAINandFINEGAIN).Notethatthedefaultgainafterresetis0dB.
Table18.Full-ScaleRangeAcrossGains
GAIN,dB
03.50.51.01.52.02.53.03.54.04.55.05.56.0
Fine(programmable)
TYPEDefaultafterresetCoarse(fixed)
FULL-SCALE,VPP
2V1.341.1.781.681.591.501.421.341.261.191.121.061.00
CLOCKINPUT
Theclockinputscanbedrivendifferentially(sine,LVPECLorLVDS)orsingle-ended(LVCMOS),withlittleornodifferenceinperformancebetweenthem.Thecommon-modevoltageoftheclockinputsissettoVCMusinginternal5kΩresistorsasshowninFigure88.Thisallowsusingtransformer-coupleddrivecircuitsforsinewaveclockorac-couplingforLVPECL,LVDSclocksources(Figure90andFigure91).Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comClockBufferLpkg»2nHCLKPCbond»1pF10WCeqResr»100W6pF5kW5kWVCMCeqLpkg»2nHCLKMCbond»1pF10WResr»100WCeq»1to3pF,equivalentinputcapacitanceofclockbufferS0275-02Figure88.InternalClockBuffer
100k10kImpedance − Ω1k10010525456585105125G083fS − Sampling Frequency − MSPSFigure.ClockInputImpedance
46SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
0.1mFCLKPDifferentialSine-WaveorPECLorLVDSClockInput0.1mFCLKMADS62P2xS0167-07Figure90.DifferentialClockDrivingCircuit
Single-endedCMOSclockcanbeac-coupledtotheCLKPinput,withCLKMconnectedtogroundwitha0.1-µFcapacitor,asshowninFigure91.0.1mFCMOSClockInputCLKP0.1mFCLKMADS62P2xS0168-11Figure91.Single-EndedClockDrivingCircuit
Forbestperformance,theclockinputshavetobedrivendifferentially,reducingsusceptibilitytocommon-modenoise.Forhighinputfrequencysampling,itisrecommendedtouseaclocksourcewithverylowjitter.Band-passfilteringoftheclocksourcecanhelpreducetheeffectofjitter.Thereisnochangeinperformancewithanon-50%dutycycleclockinput.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback47
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comPOWERDOWN
ADS62P2Xhasthreepowerdownmodes–powerdownglobal,individualchannelstandbyandindividualchanneloutputbufferdisable.ThesecanbesetusingeithertheserialregisterbitsorusingthecontrolpinsCTRL1toCTRL3.
Table19.PowerDownModes
CONFIGUREUSING
POWERDOWNMODES
Normaloperation
ChannelAoutputbufferdisabledChannelBoutputbufferdisabledChannelAandBoutputbufferdisabledChannelAandBpowereddownChannelAstandbyChannelBstandby
Multiplexed(MUX)mode–OutputdataofchannelAandBismultiplexedandavailableonDA13toDA0pins.
SERIALINTERFACE000001010011100101110111
PARALLELCONTROLPINSCTRL1lowlowlowlowhighhighhighhigh
CTRL2lowlowhighhighlowlowhighhigh
CTRL3lowhighlowhighlowhighlowhigh
—Fast(100ns)Fast(100ns)Fast(100ns)Slow(15µS)Fast(100ns)Fast(100ns)
—WAKE-UPTIME
PowerDownGlobal
Inthismode,theentirechipincludingboththeA/Dconverters,internalreferenceandtheoutputbuffersarepowereddownresultinginreducedtotalpowerdissipationofabout50mW.Theoutputbuffersareinhighimpedancestate.Thewake-uptimefromtheglobalpowerdowntodatabecomingvalidinnormalmodeistypically15µs.
ChannelStandby(IndividualorBothChannels)
ThismodeallowstheindividualADCstobepowereddown.Theinternalreferencesareactiveandthisresultsinfastwake-uptime,about100ns.Thetotalpowerdissipationinstandbyisabout482mW.OutputBufferDisable(IndividualorBothChannels)
Eachchannel’soutputbuffercanbedisabledandputinhighimpedancestate--wakeuptimefromthismodeisfast,about100ns.InputClockStop
Inadditiontotheabove,theconverterentersalow-powermodewhentheinputclockfrequencyfallsbelow1MSPS.Thepowerdissipationisabout140mW.
POWERSUPPLYSEQUENCE
Duringpower-up,theAVDDandDRVDDsuppliescancomeupinanysequence.Thetwosuppliesareseparatedinthedevice.Externally,theycanbedrivenfromseparatesuppliesorderivedfromasinglesupply.
48SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
DIGITALOUTPUTINFORMATION
ADS62P2Xprovides12bitdataperchannelandacommonoutputclocksynchronizedwiththedata.TheoutputinterfacecanbeeitherparallelCMOSorDDRLVDSvoltagelevelsandcanbeselectedusingserialregisterbitorparallelpinSEN.ParallelCMOSInterfaceIntheCMOSmode,theoutputbuffersupply(DRVDD)canbeoperatedoverawiderangefrom1.8Vto3.3V(typical).EachdatabitisoutputonseparatepinasCMOSvoltagelevel,everyclockcycle(seeFigure92).ForDRVDD>2.2V,itisrecommendedtousetheCMOSoutputclock(CLKOUT)tolatchdatainthereceivingchip.TherisingedgeofCLKOUTcanbeusedtolatchdatainthereceiver,evenatthehighestsamplingspeed.Itisrecommendedtominimizetheloadcapacitanceseenbydataandclockoutputpinsbyusingshorttracestothereceiver.Also,matchtheoutputdataandclocktracestominimizetheskewbetweenthem.
ForDRVDD<2.2V,itisrecommendedtouseexternalclock(forexample,inputclockdelayedtogetdesiredsetup/holdtimes).
CMOSOutputBuffersDA0DA1DA2DA3···12-BitChannel-ADataDA10DA11CLKOUTDB0DB1DB212-BitChannel-BDataDB3···DB10DB11B0287-02Figure92.CMOSOutputInterface
OutputBufferStrengthProgrammability
Switchingnoise(causedbyCMOSoutputdatatransitions)cancoupleintotheanaloginputsduringtheinstantofsamplinganddegradetheSNR.ThecouplingandSNRdegradationincreasesastheoutputbufferdriveismadestronger.Tominimizethis,ADS62P2XCMOSoutputbuffersaredesignedwithcontrolleddrivestrengthtogetbestSNR.Thedefaultdrivestrengthalsoensureswidedatastablewindowforloadcapacitancesupto5pFandDRVDDsupplyvoltage>2.2V.
Toensurewidedatastablewindowforloadcapacitance>5pF,thereexistsoptiontoincreasetheoutputdataandclockdrivestrengthsusingtheserialinterface(DATAOUTSTRENGTHandCLKOUTSTRENGTH).NotethatforDRVDDsupplyvoltage<2.2V,itisrecommendedtousemaximumdrivestrength(foranyvalueofloadcapacitance).
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback49
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comCMOSModePowerDissipation
WithCMOSoutputs,theDRVDDcurrentscaleswiththesamplingfrequencyandtheloadcapacitanceoneveryoutputpin.ThemaximumDRVDDcurrentoccurswheneachoutputbittogglesbetween0and1everyclockcycle.Inactualapplications,thisconditionisunlikelytooccur.TheactualDRVDDcurrentwouldbedeterminedbytheaveragenumberofoutputbitsswitching,whichisafunctionofthesamplingfrequencyandthenatureoftheanaloginputsignal.
DigitalcurrentduetoCMOSoutputswitching=CL×DRVDD×(N×FAVG),whereCL=loadcapacitance,N×FAVG=averagenumberofoutputbitsswitching.
Figure79showsthecurrentwithvariousloadcapacitancesacrosssamplingfrequenciesat2MHzanaloginputfrequency.
DDRLVDSInterface
TheLVDSinterfaceworksonlywith3.3VDRVDDsupply.Inthismode,the12databitsofeachchannelandacommonoutputclockareavailableasLVDS(LowVoltageDifferentialSignal)levels.TwosuccessivedatabitsaremultiplexedandoutputoneachLVDSdifferentialpaireveryclockcycle(DDR–DoubleDataRate,Figure94).LVDSBuffersPinsDA0PDA0MDA2PDA2M···DataBitsD0,D1DataBitsD2,D3···12-BitChannel-ADataDA10PDA10MDataBitsD10,D11CLKOUTPCLKOUB0PDB0MOutputClockDataBitsD0,D1DataBitsD2,D3···12-BitChannel-BDataDB2PDB2M···DB10PDB10MDataBitsD10,D11B0288-02Figure93.DDRLVDSOutputs
EvendatabitsD0,D2,D4,D6,D8,D10areoutputattherisingedgeofCLKOUTPandodddatabitsD1,D3,D5,D7,D9,D11areoutputatthefallingedgeofCLKOUTP.BoththerisingandfallingedgesofCLKOUTPhavetobeusedtocaptureallthedatabits.
50SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
CLKOUTMCLKOUTPDA0(DB0)D0D1D0D1DA2(DB2)D2D3D2D3DA4(DB4)D4D5D4D5DA6(DB6)D6D7D6D7DA8(DB8)D8D9D8D9DA10(DB10)D10D11D10D11SampleNSampleN+1T0110-03Figure94.DDRLVDSInterface
LVDSBufferCurrentProgrammability
ThedefaultLVDSbufferoutputcurrentis3.5mA.Whenterminatedby100Ω,thisresultsina350-mVsingle-endedvoltageswing(700-mVPPdifferentialswing).TheLVDSbuffercurrentscanalsobeprogrammedto2.5mA,4.5mA,and1.75mA(LVDSCURRENT).Inaddition,thereexistsacurrentdoublemode,wherethiscurrentisdoubledforthedataandoutputclockbuffers(registerbitsCURRENTDOUBLE).LVDSBufferInternalTermination
Aninternalterminationoptionisavailable(usingtheserialinterface),bywhichtheLVDSbuffersaredifferentiallyterminatedinsidethedevice.Theterminationresistancesavailableare–300Ω,185Ω,and150Ω(nominalwith±20%variation).Anycombinationofthesethreeterminationscanbeprogrammed;theeffectiveterminationistheparallelcombinationoftheselectedresistances.Thisresultsineighteffectiveterminationsfromopen(notermination)to60Ω.
Theinternalterminationhelpstoabsorbanyreflectionscomingfromthereceiverend,improvingthesignalintegrity.With100Ωinternaland100Ωexternaltermination,thevoltageswingatthereceiverendishalved(comparedtonointernaltermination).ThevoltageswingcanberestoredbyusingtheLVDScurrentdoublemode.Figure95andFigure96comparetheLVDSeyediagramswithoutandwith100Ωinternaltermination.Withinternaltermination,theeyelookscleanevenwith10pFloadcapacitance(fromeachoutputpintoground).Theterminationscanbeprogrammedusingregisterbits(LVDSTERMINATION).Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback51
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comFigure95.LVDSEyeDiagram–NoInternalTermination,ExternalTermination=100Ω
Figure96.LVDSEyeDiagram–With100ΩInternalTermination,Externaltermination=100ΩandLVDS
currentDoubleModeEnabled
52SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
OutputDataFormat
Twooutputdataformatsaresupported–2scomplementandstraightbinary.TheycanbeselectedusingtheserialinterfaceregisterbitorcontrollingtheSENpininparallelconfigurationmode.Intheeventofaninputvoltageoverdrive,thedigitaloutputsgototheappropriatefullscalelevel.Forapositiveoverdrive,theoutputcodeis0x7FFinoffsetbinaryoutputformat,and0x3FFin2scomplementoutputformat.Foranegativeinputoverdrive,theoutputcodeis0x000inoffsetbinaryoutputformatand0x400in2scomplementoutputformat.MultiplexedOutputmode
ThismodeisavailableonlywithCMOSinterface.Inthismode,thedigitaloutputsofboththechannelsaremultiplexedandoutputonasinglebus(DB0-DB11pins),asperthetimingdiagramshowninFigure97.ThechannelAoutputpins(DA0-DA11)arethree-stated.SincetheoutputdatarateontheDBbusiseffectivelydoubled,thismodeisrecommendedonlyforlowsamplingfrequencies(<65MSPS).
ThismodecanbeenabledusingregisterbitsorusingtheparallelpinsCTRL1,CTRL2,andCTRL3.CLKOUTDB0DA0DB0DA0DB0DB1DA1DB1DA1DB1DB2DA2DB2DA2DB2DB11DA11DB11DA11DB11SampleNSampleN+1T0297-02Figure97.MultiplexedMode–OutputTiming
LowLatencyMode
ThedefaultlatencyofADS62P2Xis14clockcycles.Forapplications,whichcannottoleratelargelatency,ADS62P2Xincludesaspecialmodewith10clockcycleslatency.Inthelowlatencycondition,theDigitalProcessingblockisbypassedanditsfeatures(offsetcorrection,finegain,decimationfilters)arenotavailable.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback53
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comDETAILSOFDIGITALPROCESSINGBLOCK
CLIPPERFromADCOutput12Bits12Bits12Bits12Bits12BitsTooutputbuffersLVDSorCMOSFineGain(0to6dB0.05dBSteps)GainCorrection(0.05dBSteps)24TAPFILTER-LOWPASS-HIGHPASS-BANDPASSDECIMATIONBY2/4/812BitsOFFSETESTIMATIONBLOCK0DisableOffsetCorrectionOFFSETCORRECTIONGAINCORRECTIONFilterSelectBypassDecimationFINEGAINDIGITALFILTERandDECIMATIONBypassFilterFreezeOffsetCorrectionDIGITALPROCESSINGBLOCKB02-02Figure98.DigitalProcessingBlockDiagram
OffsetCorrection
ADS62P2Xhasaninternaloffsetcorrectionalgorithmthatestimatesandcorrectsdcoffsetupto±10mV.Thecorrectioncanbeenabledusingtheserialregisterbit(OFFSETLOOPEN).Onceenabled,thealgorithmestimatesthechanneloffsetandappliesthecorrectioneveryclockcycle.Thetimeconstantofthecorrectionloopisafunctionofthesamplingclockfrequency.Thetimeconstantcanbecontrolledusingregisterbits(OFFSETLOOPTC)asdescribedinTable20.Table20.TimeConstantofOffsetCorrectionAlgorithm
D6-D5-D4
000001010011100101110111
(1)
Samplingfrequency,Fs=125MSPS
TIMECONSTANT(TCCLK),Numberofclockcycles
2272222
26252428
TIMECONSTANT,sec(=TCCLK×1/Fs)(1)
1.10.550.270.132.154.31.11.1
229227227
Itisalsopossibletofreezetheoffsetcorrectionusingtheserialinterface().Oncefrozen,theoffsetestimationbecomesinactiveandthelastestimatedvalueisusedforcorrectioneveryclockcycle.Notethattheoffsetcorrectionisdisabledbydefaultafterreset.Figure99showsthetimeresponseoftheoffsetcorrectionalgorithm,afteritisenabled(forclarity,anexamplewithnoappliedinputsignalisshown).Afewtimeconstantsafterthecorrectionisenabled,theoffsetgetscancelledandtheoutputcodeapproachestheidealvalueof2048.
54SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
206520602055Device WithOffset CancelledCode − LSB2050204520402035203002468101214G084Offset LoopEnabled HereDevice WithInitial Offsett − Time − sFigure99.TimeResponseofOffsetCorrection
GainCorrection
ADS62P2XhasabilitytomakefinecorrectionstotheADCchannelgain.Thecorrectionscanbedoneinstepsof0.05dB,uptoamaximumof0.5dB,usingtheregisterbits(GAINCORRECTION).Onlypositivecorrectionsaresupportedandthesamecorrectionappliestoboththechannels.Table21.GainCorrectionValues
D3-D2-D1-D0
00000001001000110100010101100111100010011010
Othercombinations
AMOUNTOFCORRECTION,
dB
0+0.05+0.1+0.15+0.20+0.25+0.30+0.35+0.40+0.45+0.5Unused
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback55
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comDecimationFilters
ADS62P2XincludesoptiontodecimatetheADCoutputdatawithin-builtlow-pass,high-pass,orband-passfilters.
Thedecimationrateandtypeoffiltercanbeselectedusingregisterbits(DECIMATIONRATE)and(DECIMATIONFILTERTYPE).Decimationratesof2,4,or8areavailableandeitherlow-pass,high-pass,orband-passfilterscanbeselected(seeTable22).Bydefault,thedecimationfilterisdisabled–useregisterbittoenableit.Table22.DecimationFilterModes
COMBINATIONOFDECIMATIONRATESANDFILTERTYPES
DECIMATIONDecimateby2Decimateby4
TYPEOFFILTER
In-builtlow-passfilter(passband=0toFs/4)In-builthigh-passfilter(passband=Fs/4toFs/2)In-builtlow-passfilter(passband=0toFs/8)In-built2ndband-passfilter(passband=Fs/8toFs/4)In-built3rdband-passfilter(passband=Fs/4to3Fs/8)In-builtlastband-passfilter(passband=3Fs/8toFs/2)
Decimateby2Decimateby4Decimateby8NOdecimation
Customfilter(userprogrammablecoefficients)Customfilter(userprogrammablecoefficients)Customfilter(userprogrammablecoefficients)Customfilter(userprogrammablecoefficients)
RATE>00000000100000000001
0011110101
000011XXXX010101XXXX
>0000001111
1111111110
DecimationFilterEquation
Thedecimationfilterisimplementedas24-tapFIRwithsymmetricalcoefficients(eachcoefficientis12-bitsigned).Thefilterequationis:
y(n)+ǒ21Ǔ [h0 x(n))h1 x(n*1))h2 x(n*2))AAA)h11 x(n*11))h11 x(n*12))AAA)h1 x(n*22))h0 x(n*23)]11(3)
Bysettingtheregisterbit=1,a23-tapFIRisimplemented:y(n)+ǒ21Ǔx[h0 x(n))h1 x(n*1))h2 x(n*2))AAA)h10 x(n*10))h11 x(n*11))h10 x(n*12))AAA)h1 x(n*21))h0 x(n*22)]11(4)
Intheaboveequations,
h0,h1…h11are12-bitsignedrepresentationofthecoefficients,x(n)istheinputdatasequencetothefiltery(n)isthefilteroutputsequencePre-definedCoefficients
Thein-builtfiltertypes(low-pass,high-pass,andband-pass)usepre-definedcoefficients.Thefrequencyresponseofthein-builtfiltersisshowninFigure100andFigure101.56SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
50−5−10−15−20−25−30−35−40−450.00.10.20.30.40.5G085Magnitude − dBLow PassHigh PassNormalized Frequency − f/fSFigure100.Decimateby2FilterResponse
50−5−10−15−20−25−30−35−40−450.00.10.20.30.40.5G086Magnitude − dBLow PassHigh PassNormalized Frequency − f/fSFigure101.Decimateby4FilterResponse
50−5−10−15−20−25−30−35−40−450.02nd Bandpass0.10.20.30.40.5G087Magnitude − dB1st BandpassNormalized Frequency − f/fSFigure102.Decimateby4Band-PassResponse
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback57
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comTable23.PredefinedCoefficientsforDecimationby2Filters
COEFFICIENTS
LOW-PASSFILTER
h0h1h2h3h4h5h6h7h8h9h10h11
23-37-668-36-6135118-100-197273943
DECIMATEBY2
HIGH-PASSFILTER
-22-65-523066-35-10738202-41-41061
Table24.PredefinedCoefficientsforDecimationby4Filters
COEFFICIENTS
LOW-PASSFILTER
h0h1h2h3h4h5h6h7h8h9h10h11
-17-50714624-42-100-978202414554
-719-4712773086117-190-4-113526
DECIMATEBY4
1stBAND-PASSFILTER
2NDBAND-PASSFILTER
-34-34-1014358-28-5-17929486-563352
HIGH-PASSFILTER
32-15-9522-8-81106-62-97310-501575
CustomFilterCoefficientswithDecimation
Thefiltercoefficientscanalsobeprogrammedbytheuser(custom).Forcustomcoefficients,settheregisterbit(FILTERCOEFFSELECT)andloadthecoefficients(h0toh11)inregisters1Eto2Fusingtheserialinterface(Table25)as:Registercontent=12bitsignedrepresentationof[realcoefficientvalue×211]
58SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
CustomFilterCoefficientswithoutDecimation
Thefilterwithcustomcoefficientscanalsobeusedwiththedecimationmodedisabled.Inthismode,thefilterimplementationis12-tapFIR:
y(n)+ǒ21Ǔx[h6 x(n))h7 x(n*1))h8 x(n*2))AAA)h11 x(n*5))h11 x(n*6))AAA)h7 x(n*10))h6 x(n*11)]11(5)
Table25.RegisterMapofCustomCoefficients
A7–A0(hex)1E1F202122232425262728292A2B2C2D2E2FCoefficienth11<3:0>Coefficienth11<11:4>Coefficienth9<3:0>Coefficienth9<11:4>Coefficienth10<7:0>Coefficienth10<11:8>Coefficienth7<3:0>Coefficienth7<11:4>Coefficienth8<7:0>Coefficienth8<11:8>Coefficienth5<3:0>Coefficienth5<11:4>Coefficienth6<7:0>Coefficienth6<11:8>Coefficienth3<3:0>Coefficienth3<11:4>Coefficienth4<7:0>Coefficienth4<11:8>Coefficienth1<3:0>Coefficienth1<11:4>Coefficienth2<7:0>Coefficienth2<11:8>D7D6D5D4D3D2D1D0Coefficienth0<7:0>Coefficienth0<11:8>Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback59
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comBOARDDESIGNCONSIDERATIONSGrounding
Asinglegroundplaneissufficienttogivegoodperformance,providedtheanalog,digital,andclocksectionsoftheboardarecleanlypartitioned.SeetheEVMUserGuide(SLAU237)fordetailsonlayoutandgrounding.SupplyDecoupling
AsADS62P2Xalreadyincludesinternaldecoupling,minimalexternaldecouplingcanbeusedwithoutlossinperformance.Notethatdecouplingcapacitorscanhelpfilterexternalpowersupplynoise,sotheoptimumnumberofcapacitorswoulddependontheactualapplication.Thedecouplingcapacitorsshouldbeplacedveryclosetotheconvertersupplypins.
Itisrecommendedtouseseparatesuppliesfortheanaloganddigitalsupplypinstoisolatedigitalswitchingnoisefromsensitiveanalogcircuitry.Incaseonlyasingle3.3-Vsupplyisavailable,itshouldberoutedfirsttoAVDD.Itcanthenbetappedandisolatedwithaferritebead(orinductor)withdecouplingcapacitor,beforebeingroutedtoDRVDD.ExposedThermalPad
Itisnecessarytosoldertheexposedpadatthebottomofthepackagetoagroundplaneforbestthermalperformance.Fordetailedinformation,seeapplicationnotesQFNLayoutGuidelines(SLOA122)andQFN/SONPCBAttachment(SLUA271).60SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
DEFINITIONOFSPECIFICATIONS
AnalogBandwidth
Theanaloginputfrequencyatwhichthepowerofthefundamentalisreducedby3dBwithrespecttothelowfrequencyvalue.
ApertureDelay
Thedelayintimebetweentherisingedgeoftheinputsamplingclockandtheactualtimeatwhichthesamplingoccurs.
ApertureUncertainty(Jitter)
Thesample-to-samplevariationinaperturedelay.
ClockPulseWidth/DutyCycle
Thedutycycleofaclocksignalistheratioofthetimetheclocksignalremainsatalogichigh(clockpulsewidth)totheperiodoftheclocksignal.Dutycycleistypicallyexpressedasapercentage.Aperfectdifferentialsine-waveclockresultsina50%dutycycle.
MaximumConversionRate
Themaximumsamplingrateatwhichcertifiedoperationisgiven.Allparametrictestingisperformedatthissamplingrateunlessotherwisenoted.
MinimumConversionRate
TheminimumsamplingrateatwhichtheADCfunctions.
DifferentialNonlinearity(DNL)
AnidealADCexhibitscodetransitionsatanaloginputvaluesspacedexactly1LSBapart.TheDNListhedeviationofanysinglestepfromthisidealvalue,measuredinunitsofLSBs
IntegralNonlinearity(INL)
TheINListhedeviationoftheADC’stransferfunctionfromabestfitlinedeterminedbyaleastsquarescurvefitofthattransferfunction,measuredinunitsofLSBs.
GainError
GainerroristhedeviationoftheADC'sactualinputfull-scalerangefromitsidealvalue.Thegainerrorisgivenasapercentageoftheidealinputfull-scalerange.Gainerrorhastwocomponents:errorduetoreferenceinaccuracyanderrorduetothechannel.BoththeseerrorsarespecifiedindependentlyasEGREFandEGCHAN.Toafirstorderapproximation,thetotalgainerrorwillbeETOTAL~EGREF+EGCHAN
Forexample,ifETOTAL=±0.5%,thefull-scaleinputvariesfrom(1-0.5/100)xFSidealto(1+0.5/100)xFSideal.
OffsetError
Theoffseterroristhedifference,giveninnumberofLSBs,betweentheADC’sactualaverageidlechanneloutputcodeandtheidealaverageidlechanneloutputcode.ThisquantityisoftenmappedintomV.
TemperatureDrift
Thetemperaturedriftcoefficient(withrespecttogainerrorandoffseterror)specifiesthechangeperdegreeCelsiusoftheparameterfromTMINtoTMAX.ItiscalculatedbydividingthemaximumdeviationoftheparameteracrosstheTMINtoTMAXrangebythedifferenceTMAX–TMIN.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback61
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
ADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
www.ti.comSignal-to-NoiseRatio
SNRistheratioofthepowerofthefundamental(PS)tothenoisefloorpower(PN),excludingthepoweratdcandthefirstnineharmonics.
PSNR+10Log10sPN(6)
SNRiseithergiveninunitsofdBc(dBtocarrier)whentheabsolutepowerofthefundamentalisusedasthereference,ordBFS(dBtofullscale)whenthepowerofthefundamentalisextrapolatedtotheconverter’sfull-scalerange.
Signal-to-NoiseandDistortion(SINAD)
SINADistheratioofthepowerofthefundamental(PS)tothepowerofalltheotherspectralcomponentsincludingnoise(PN)anddistortion(PD),butexcludingdc.
PsSINAD+10Log10PN)PD(7)SINADiseithergiveninunitsofdBc(dBtocarrier)whentheabsolutepowerofthefundamentalisusedasthereference,ordBFS(dBtofullscale)whenthepowerofthefundamentalisextrapolatedtotheconverter’sfull-scalerange.
EffectiveNumberofBits(ENOB)
TheENOBisameasureofaconverter’sperformanceascomparedtothetheoreticallimitbasedonquantizationnoise.
ENOB+SINAD*1.766.02(8)
TotalHarmonicDistortion(THD)
THDistheratioofthepowerofthefundamental(PS)tothepowerofthefirstnineharmonics(PD).PTHD+10Log10sPNTHDistypicallygiveninunitsofdBc(dBtocarrier).
(9)
Spurious-FreeDynamicRange(SFDR)
Theratioofthepowerofthefundamentaltothehighestotherspectralcomponent(eitherspurorharmonic).SFDRistypicallygiveninunitsofdBc(dBtocarrier).
Two-ToneIntermodulationDistortion
IMD3istheratioofthepowerofthefundamental(atfrequenciesf1andf2)tothepoweroftheworstspectralcomponentateitherfrequency2f1–f2or2f2–f1.IMD3iseithergiveninunitsofdBc(dBtocarrier)whentheabsolutepowerofthefundamentalisusedasthereference,ordBFS(dBtofullscale)whenthepowerofthefundamentalisextrapolatedtotheconverter’sfull-scalerange.
DCPowerSupplyRejectionRatio(DCPSRR)
TheDCPSSRistheratioofthechangeinoffseterrortoachangeinanalogsupplyvoltage.TheDCPSRRistypicallygiveninunitsofmV/V.
62SubmitDocumentationFeedbackCopyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
www.ti.comADS62P25,ADS62P24ADS62P23,ADS62P22SLAS576A–OCTOBER2007–REVISEDFEBRUARY2008
ACPowerSupplyRejectionRatio(ACPSRR)
ACPSRRisthemeasureofrejectionofvariationsinthesupplyvoltageoftheADC.IfΔVSUPisthechangeinthesupplyvoltageandΔVOUTistheresultantchangeintheADCoutputcode(referredtotheinput),then
DVOUT(ExpressedindBc)PSRR=20Log10DVSUP(10)
CommonModeRejectionRatio(CMRR)
CMRRisthemeasureofrejectionofvariationsintheinputcommon-modevoltageoftheADC.IfΔVcmisthe
changeintheinputcommon-modevoltageandΔVOUTistheresultantchangeintheADCoutputcode(referredtotheinput),then
10DVOUT(ExpressedindBc)CMRR=20LogDVCM(11)
VoltageOverloadRecovery
Thenumberofclockcyclestakentorecovertolessthan1%errorfora6-dBoverloadontheanaloginputs.A
6-dBFSsinewaveatNyquistfrequencyisusedastheteststimulus.
Copyright©2007–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback63
ProductFolderLink(s):ADS62P25,ADS62P24ADS62P23,ADS62P22
元器件交易网www.cecb2b.com
PACKAGEOPTIONADDENDUM
www.ti.com
20-Mar-2008
PACKAGINGINFORMATION
OrderableDeviceADS62P22IRGCRADS62P22IRGCRG4ADS62P22IRGCTADS62P22IRGCTG4ADS62P23IRGCRADS62P23IRGCRG4ADS62P23IRGCTADS62P23IRGCTG4ADS62P24IRGCRADS62P24IRGCRG4ADS62P24IRGCTADS62P24IRGCTG4ADS62P25IRGCRADS62P25IRGCRG4ADS62P25IRGCTADS62P25IRGCTG4
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFN
PackageDrawingRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGCRGC
PinsPackageEcoPlan(2)
Qty
2500Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HR
2500Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2500Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2500Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
Addendum-Page1
元器件交易网www.cecb2b.com
PACKAGEOPTIONADDENDUM
www.ti.com
20-Mar-2008
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
Addendum-Page2
元器件交易网www.cecb2b.com
PACKAGEMATERIALSINFORMATION
www.ti.com
3-Jul-2008
TAPEANDREELINFORMATION
*Alldimensionsarenominal
Device
PackagePackagePinsTypeDrawingVQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFN
RGCRGCRGCRGCRGCRGCRGCRGC
SPQ
ReelReelDiameterWidth(mm)W1(mm)330.0330.0330.0330.0330.0330.0330.0330.0
16.416.416.416.416.416.416.416.4
A0(mm)B0(mm)K0(mm)
P1(mm)12.012.012.012.012.012.012.012.0
WPin1(mm)Quadrant16.016.016.016.016.016.016.016.0
Q2Q2Q2Q2Q2Q2Q2Q2
ADS62P22IRGCRADS62P22IRGCTADS62P23IRGCRADS62P23IRGCTADS62P24IRGCRADS62P24IRGCTADS62P25IRGCRADS62P25IRGCT
2500250250025025002502500250
9.39.39.39.39.39.39.39.3
9.39.39.39.39.39.39.39.3
1.51.51.51.51.51.51.51.5
PackMaterials-Page1
元器件交易网www.cecb2b.com
PACKAGEMATERIALSINFORMATION
www.ti.com
3-Jul-2008
*Alldimensionsarenominal
DeviceADS62P22IRGCRADS62P22IRGCTADS62P23IRGCRADS62P23IRGCTADS62P24IRGCRADS62P24IRGCTADS62P25IRGCRADS62P25IRGCT
PackageType
VQFNVQFNVQFNVQFNVQFNVQFNVQFNVQFN
PackageDrawing
RGCRGCRGCRGCRGCRGCRGCRGC
Pins
SPQ2500250250025025002502500250
Length(mm)
333.2333.2333.2333.2333.2333.2333.2333.2
Width(mm)345.9345.9345.9345.9345.9345.9345.9345.9
Height(mm)
28.628.628.628.628.628.628.628.6
PackMaterials-Page2
元器件交易网www.cecb2b.com
元器件交易网www.cecb2b.com
元器件交易网www.cecb2b.com
元器件交易网www.cecb2b.com
IMPORTANTNOTICE
TexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,modifications,enhancements,improvements,andotherchangestoitsproductsandservicesatanytimeandtodiscontinueanyproductorservicewithoutnotice.Customersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete.AllproductsaresoldsubjecttoTI’stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment.
TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’sstandardwarranty.TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthiswarranty.Exceptwheremandatedbygovernmentrequirements,testingofallparametersofeachproductisnotnecessarilyperformed.
TIassumesnoliabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand
applicationsusingTIcomponents.Tominimizetherisksassociatedwithcustomerproductsandapplications,customersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanyTIpatentright,copyright,maskworkright,orotherTIintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensefromTItousesuchproductsorservicesorawarrantyorendorsementthereof.Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.Reproductionofthisinformationwithalterationisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforsuchaltereddocumentation.Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforanysuchstatements.
TIproductsarenotauthorizedforuseinsafety-criticalapplications(suchaslifesupport)whereafailureoftheTIproductwouldreasonablybeexpectedtocauseseverepersonalinjuryordeath,unlessofficersofthepartieshaveexecutedanagreementspecificallygoverningsuchuse.Buyersrepresentthattheyhaveallnecessaryexpertiseinthesafetyandregulatoryramificationsoftheirapplications,and
acknowledgeandagreethattheyaresolelyresponsibleforalllegal,regulatoryandsafety-relatedrequirementsconcerningtheirproductsandanyuseofTIproductsinsuchsafety-criticalapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.Further,BuyersmustfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofTIproductsinsuchsafety-criticalapplications.
TIproductsareneitherdesignednorintendedforuseinmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsarespecificallydesignatedbyTIasmilitary-gradeor\"enhancedplastic.\"OnlyproductsdesignatedbyTIasmilitary-grademeetmilitary
specifications.BuyersacknowledgeandagreethatanysuchuseofTIproductswhichTIhasnotdesignatedasmilitary-gradeissolelyattheBuyer'srisk,andthattheyaresolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.TIproductsareneitherdesignednorintendedforuseinautomotiveapplicationsorenvironmentsunlessthespecificTIproductsaredesignatedbyTIascompliantwithISO/TS16949requirements.Buyersacknowledgeandagreethat,iftheyuseanynon-designatedproductsinautomotiveapplications,TIwillnotberesponsibleforanyfailuretomeetsuchrequirements.
FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions:ProductsAmplifiers
DataConvertersDSP
ClocksandTimersInterfaceLogic
PowerMgmtMicrocontrollersRFID
RF/IFandZigBee®Solutions
amplifier.ti.comdataconverter.ti.comdsp.ti.comwww.ti.com/clocksinterface.ti.comlogic.ti.compower.ti.commicrocontroller.ti.comwww.ti-rfid.comwww.ti.com/lprfApplicationsAudio
AutomotiveBroadbandDigitalControlMedicalMilitary
OpticalNetworkingSecurityTelephony
Video&ImagingWireless
www.ti.com/audiowww.ti.com/automotivewww.ti.com/broadbandwww.ti.com/digitalcontrolwww.ti.com/medicalwww.ti.com/militarywww.ti.com/opticalnetworkwww.ti.com/securitywww.ti.com/telephonywww.ti.com/videowww.ti.com/wirelessMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265
Copyright©2008,TexasInstrumentsIncorporated
