ADSP-2191M资料

a

PERFORMANCE FEATURES

6.25ns Instruction Cycle Time, for up to 160MIPS Sustained Performance

ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic SyntaxSingle-Cycle Instruction Execution

Single-Cycle Context Switch between Two Sets of Com- putation and Memory Instructions

Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle

DSP Microcomputer

ADSP-2191M

Multifunction Instructions

Pipelined Architecture Supports Efficient Code Execution

Architectural Enhancements for Compiled C and C++ CodeEfficiency

Architectural Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, and Peripherals

Flexible Power Management with User-Selectable Power-Down and Idle Modes

FUNCTIONAL BLOCK DIAGRAM

INTERNALMEMORYFOURINDEPENDENTBLOCKSADSP-219xDSPCORECACHE؋24-BIT24BITADDRESSDATA24BITADDRESSDATA16BITDATAADDRESS16BITDATAADDRESSBLOCK0BLOCK1BLOCK2BLOCK3JTAGTEST&EMULATION6DAG14؋4؋16DAG24؋4؋16PROGRAMSEQUENCER24I/OADDRESS18EXTERNALPORTPMADDRESSBUSDMADDRESSBUS2422ADDRBUSMUX24DMACONNECTPMDATABUSPXDMDATABUS1624DMAADDRESS24DMADATA16DATABUSMUX16I/ODATAI/OPROCESSORDATAREGISTERFILEINPUTREGISTERSRESULTREGISTERSMULT16؋16-BITBARRELSHIFTERALUI/OREGISTERS(MEMORY-MAPPED)CONTROLSTATUSBUFFERSDMACONTROLLER24HOSTPORT18SERIALPORTS(3)6SPIPORTS(2)2UARTPORT(1)SYSTEMINTERRUPTCONTROLLERPROGRAMMABLEFLAGS(16)3TIMERS(3)REV. 0

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.Tel:781/329-4700 www.analog.comFax:781/326-8703 © Analog Devices, Inc., 2002

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ADSP-2191M

INTEGRATION FEATURES

160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAMDual-Purpose 24-Bit Memory for Both Instruction and Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators

Unified Memory Space Allows Flexible Address Genera- tion, Using Two Independent DAG Units

Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution

Enhanced Interrupt Controller Enables Programming of Interrupt Priorities and Nesting Modes

SYSTEM INTERFACE FEATURES

Host Port with DMA Capability for Glueless 8- or 16-Bit Host Interface

16-Bit External Memory Interface for up to 16M Words of Addressable Memory Space

Three Full-Duplex Multichannel Serial Ports, with

Support for H.100 and up to 128 TDM Channels with A-Law and ␮-Law Companding Optimized for Telecom- munications Systems

Two SPI-Compatible Ports with DMA SupportUART Port with DMA Support

16 General-Purpose I/O Pins with Integrated Inter-rupt Support

Three Programmable Interval Timers with PWM

Generation, PWM Capture/Pulsewidth Measurement, and External Event Counter Capabilities

Up to 11 DMA Channels Can Be Active at Any Given Time for High I/O Throughput

On-Chip Boot ROM for Automatic Booting from External 8- or 16-Bit Host Device, SPI ROM, or UART with Autobaud Detection

Programmable PLL Supports 1؋ to 32؋ Input Frequency Multiplication and Can Be Altered during RuntimeIEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging2.5V Internal Operation and 3.3V I/O

144-Lead LQFP and 144-Ball Mini-BGA Packages

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12Instruction Set Description . . . . . . . . . . . . . . . . . . . .13Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13Additional Information . . . . . . . . . . . . . . . . . . . . . . .15PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Environmental Conditions . . . . . . . . . . . . . . . . . . . .42144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49

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ADSP-2191M

GENERAL DESCRIPTION

The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address gener-ators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhance-ments to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program.Indirect addressing options provide addressing flexibility—premodify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering.The ADSP-2191M integrates K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages.Fabricated in a high-speed, low-power, CMOS process, the ADSP-2191M operates with a 6.25ns instruction cycle time (160MIPS). All instructions, except single-word instructions, execute in one processor.The ADSP-2191M’s flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2191M can:•Generate an address for the next instruction fetch•Fetch the next instruction•Perform one or two data moves

•Update one or two data address pointers•Perform a computational operation

These operations take place while the processor continuesto:•Receive and transmit data through two serial ports•Receive and/or transmit data from a Host•Receive or transmit data through the UART•Receive or transmit data over two SPI ports

•Access external memory through the external memory interface

•Decrement the timers

DSP Core Architecture

uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.The functional block diagram onpage1 shows the architecture of the ADSP-219x core. It contains three independent compu-tational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision com-putations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multi-ply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arith-metic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations.Register-usage rules influence placement of input and results within the computational units. For most operations, the com-putational units’ data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more infor-mation, see the ADSP-219x DSP Instruction Set Reference.A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subrou-tine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2191M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within K word bound-aries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch. Efficient data transfer in the core is achieved with the use of internal buses:•Program Memory Address (PMA) Bus•Program Memory Data (PMD) Bus•Data Memory Address (DMA) Bus•Data Memory Data (DMD) Bus•DMA Address Bus•DMA Data Bus

The ADSP-2191M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2191M assembly language REV. 0

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ADSP-2191M

The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Boot memory space and I/O memory space also share the external buses.Program memory can store both instructions and data, permit-ting the ADSP-2191M to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP’s dual memory buses also let the ADSP-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle.DSP Peripherals Architecture

ADSP-2191MCLOCKORCRYSTALTIMEROUTORCAPTURECLOCKMULTIPLYANDRANGEBOOTANDOPMODECLKINXTALTMR2–0CLKOUTADDR21–0DATA15–8DATA7–0MS3–0MSEL6–0/PF6–0DF/PF7BYPASSBMODE1–0OPMODERDWRACKADDRESSCONTROLDATAEXTERNALMEMORY(OPTIONAL)ADDR21–0DATA15–8DATA7–0CSOEWEACKBOOTMEMORY(OPTIONAL)The functional block diagram onpage1 shows the DSP’s on-chip peripherals, which include the external memory inter-face, Host port, serial ports, SPI-compatible ports, UART port, JTAG test and emulation port, timers, flags, and interrupt con-troller. These on-chip peripherals can connect to off-chip devices as shown in Figure1.The ADSP-2191M has a 16-bit Host port with DMA capability that lets external Hosts access on-chip memory. This 24-pin parallel port consists of a 16-pin multiplexed data/address bus and provides a low-service overhead data move capability. Con-figurable for 8 or 16 bits, this port provides a glueless interface to a wide variety of 8- and 16-bit microcontrollers. Two chip-selects provide Hosts access to the DSP’s entire memory map. The DSP is bootable through this port.The ADSP-2191M also has an external memory interface that is shared by the DSP’s core, the DMA controller, and DMA capable peripherals, which include the UART, SPORT0, SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external port consists of a 16-bit data bus, a 22-bit address bus, and control signals. The data bus is configurable to provide an 8 or 16bit interface to external memory. Support for word packing lets the DSP access 16- or 24-bit words from external memory regardless of the external data bus width. When configured for an 8-bit interface, the unused eight lines provide eight program-mable, bidirectional general-purpose Programmable Flag lines, six of which can be mapped to software condition signals. The memory DMA controller lets the ADSP-2191M move data and instructions from between memory spaces: internal-to-exter-nal, internal-to-internal, and external-to- external. On-chip peripherals can also use this controller for DMA transfers. The ADSP-2191M can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power-down), two external (emulator and reset), and twelve user-defined (peripherals) interrupts. The programmer assigns a peripheral to one of the 12 user-defined interrupts. The priority of each peripheral for interrupt service is determined by these assignments. There are three serial ports on the ADSP-2191M that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of opera-SPORT0TCLK0TFS0SERIALDEVICE(OPTIONAL)ADDR21–0DATA15–8DATA7–0BMSCSOEWEACKBRBGBGHEXTERNALI/OMEMORY(OPTIONAL)DT0RCLK0RFS0DR0SPORT1TCLK1TFS1SERIALDEVICE(OPTIONAL)DT1RCLK1RFS1DR1SPORT2TCLK2/SCK0TFS2/MOSI0SPI0IOMSADDR17–0DATA15–8DATA7–0CSOEWEACKHOSTPROCESSORSPI1HAD15–0HA16(OPTIONAL)SERIALDEVICE(OPTIONAL)DT2/MISO0RCLK2/SCK1RFS2/MOSI1DR2/MISO1ADDR15–0/DATA15–0ADDR16CS0CS1RDWRACKALEUARTUARTDEVICE(OPTIONAL)HCMSHCIOMSHRDHWRRXDTXDRESET6JTAGHACKHALEHACK_PFigure 1.System Diagram

tion. Each serial port can transmit or receive an internal or external, programmable serial clock and frame syncs. Each serial port supports 128-channel Time Division Multiplexing.The ADSP-2191M provides up to sixteen general-purpose I/O pins, which are programmable as either inputs or outputs. Eight of these pins are dedicated-general purpose Programmable Flag pins. The other eight of them are multifunctional pins, acting as general-purpose I/O pins when the DSP connects to an 8-bit external data bus and acting as the upper eight data pins when the DSP connects to a 16-bit external data bus. These Program-mable Flag pins can implement edge- or level-sensitive interrupts, some of which can be used to base the execution of conditional instructions.–4–REV. 0

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ADSP-2191M

Three programmable interval timers generate periodic inter-rupts. Each timer can be independently set to operate in one of three modes:•Pulse Waveform Generation mode•Pulsewidth Count/Capture mode•External Event Watchdog mode

Each timer has one bidirectional pin and four registers that implement its mode of operation: A 7-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulsewidth register. A single status register supports all three timers. A bit in each timer’s configuration register enables or disables the corresponding timer independently of the others. Memory Architecture

internal and external memory space, the ADSP-2191M can address two additional and separate off-chip memory spaces: I/O space and boot space. As shown in Figure2, the DSP’s two internal memory blocks populate all of Page0. The entire DSP memory map consists of 256 pages (Pages 0−255), and each page is K words long. External memory space consists of four memory banks (banks 0–3) and supports a wide variety of SRAM memory devices. Each bank is selectable using the memory select pins (MS3–0) and has configurable page boundaries, waitstates, and waitstate modes. The 1K word of on-chip boot-ROM populates the top of Page255 while the remaining 254 pages are addressable off-chip. I/O memory pages differ from external memory pages in that I/O pages are 1K word long, and the external I/O pages have their own select pin (IOMS). Pages 0–7 of I/O memory space reside on-chip and contain the configuration registers for the peripher-als. Both the core and DMA-capable peripherals can access the DSP’s entire memory map.The ADSP-2191M DSP provides K words of on-chip SRAM memory. This memory is divided into four 16K blocks located on memory Page0 in the DSP’s memory map. In addition to the KWORDMEMORYPAGESINTERNALMEMORYRESERVEDPAGE255BOOTROM,24-BITLOGICALADDRESS0؋FFFFFF0؋FF04000؋FF03FF0؋FF0000LOWERPAGEBOUNDARIESARECONFIGURABLEFORBANKSOFEXTERNALMEMORY.BOUNDARIESSHOWNAREBANKSIZESATRESET.MEMORYSELECTS(MS)FORPORTIONSOFTHEMEMORYMAPAPPEARWITHTHESELECTEDMEMORY.PAGES192–254BANK3(MS3)0؋C00000BANK2(MS2)0؋800000BANK1(MS1)0؋400000BANK0(MS0)0؋010000BLOCK3,16-BIT0؋00C0000؋0080000؋0040000؋0000008-BIT10-BITINTERNALPAGES1–2540؋010000EXTERNAL(IOMS)0؋080000؋073FF0؋00000PAGES128–191EXTERNALMEMORY(16-BIT)PAGES–127BOOTMEMORY16-BIT(BMS)KWORDI/OMEMORY16-BITLOGICALADDRESS0؋FEFFFF1KWORDPAGES8–2551KWORDPAGES0–7LOGICALADDRESS0؋FF3FFPAGES1–63INTERNALMEMORYPAGE0BLOCK2,16-BITBLOCK1,24-BITBLOCK0,24-BITFigure 2.Memory MapInternal (On-Chip) Memory

The ADSP-2191M’s unified program and data memory space consists of 16M locations that are accessible through two 24-bit address buses, the PMA and DMA buses. The DSP uses slightly REV. 0–5–

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ADSP-2191M

different mechanisms to generate a 24-bit address for each bus. The DSP has three functions that support access to the full memory map.•The DAGs generate 24-bit addresses for data fetches from the entire DSP memory address range. Because DAG index (address) registers are 16 bits wide and hold the lower 16bits of the address, each of the DAGs has its own 8-bit page register (DMPGx) to hold the most significant eight address bits. Before a DAG generates an address, the program must set the DAG’s DMPGx register to the appropriate memory page.

•The Program Sequencer generates the addresses for instruction fetches. For relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit Program Counter (PC). In direct addressing instructions (two-word instructions), the instruction provides an immediate 24-bit address value. The PC allows linear addressing of the full 24-bit address range.

•For indirect jumps and calls that use a 16-bit DAG address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page (IJPG) register to supply the most significant eight

address bits. Before a cross page jump or call, the program must set the program sequencer’s IJPG register to the appropriate memory page.

The ADSP-2191M has 1K word of on-chip ROM that holds boot routines. If peripheral booting is selected, the DSP starts executing instructions from the on-chip boot ROM, which starts the boot process from the selected peripheral. For more informa-tion, see “Booting Modes” on page11. The on-chip boot ROM is located on Page255 in the DSP’s memory space map.External (Off-Chip) Memory

External Memory Space

External memory space consists of four memory banks. These banks can contain a configurable number of K word pages. At reset, the page boundaries for external memory have Bank0 containing pages1−63, Bank1 containing pages−127, Bank2 containing pages128−191, and Bank3 that contains pages192−254. The MS3–0 memory bank pins select Banks 3–0, respectively. The external memory interface is byte-addressable and decodes the 8 MSBs of the DSP program address to select one of the four banks. Both the ADSP-219x core and DMA-capa-ble peripherals can access the DSP’s external memory space.I/O Memory Space

The ADSP-2191M supports an additional external memory called I/O memory space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports a total of 256K locations. The first 8K addresses are reserved for on-chip peripherals. The upper 248K addresses are available for external peripheral devices. The DSP’s instruc-tion set provides instructions for accessing I/O space. These instructions use an 18-bit address that is assembled from an 8-bit I/O page (IOPG) register and a 10-bit immediate value supplied in the instruction. Both the ADSP-219x core and a Host (through the Host Port Interface) can access I/O memory space.Boot Memory Space

Boot memory space consists of one off-chip bank with 63 pages. The BMS memory bank pin selects boot memory space. Both the ADSP-219x core and DMA-capable peripherals can access the DSP’s off-chip boot memory space. After reset, the DSP always starts executing instructions from the on-chip boot ROM. Depending on the boot configuration, the boot ROM code can start booting the DSP from boot memory. For more information, see “Booting Modes” on page11.Interrupts

Each of the ADSP-2191M’s off-chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. The access parameters include read and write wait counts, waitstate completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width. The core clock and peripheral clock ratios influence the external memory access strobe widths. For more information, see “Clock Signals” on page11. The off-chip memory spacesare:•External memory space (MS3–0 pins)•I/O memory space (IOMS pin)•Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through the External Port, which can be configured for data widths of 8 or 16 bits.The interrupt controller lets the DSP respond to 17 interrupts with minimum overhead. The controller implements an interrupt priority scheme as shown in Table1. Applications can use the unassigned slots for software and peripheral interrupts. Table2 shows the ID and priority at reset of each of the periph-eral interrupts. To assign the peripheral interrupts a different priority, applications write the new priority to their correspond-ing control bits (determined by their ID) in the Interrupt Priority Control register. The peripheral interrupt’s position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table1. Because the IMASK and IRPTL registers are limited to 16 bits, any peripheral interrupts –6–REV. 0

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ADSP-2191M

assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x0001E0. Table 1.Interrupt Priorities/Addresses Interrupt

IMASK/IRPTL

Vector Address1

The Interrupt Control (ICNTL) register controls interrupt nesting and enables or disables interrupts globally.The general-purpose Programmable Flag (PFx) pins can be con-figured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. Programmable Flag pin interrupts can be configured for level-sensitive, single edge-sensitive, or dual edge-sensitiveoperation. Table 3.Interrupt Control (ICNTL) Register Bits Bit

Description

Emulator (NMI)—Highest PriorityReset (NMI)

Power-Down (NMI)Loop and PC StackEmulation Kernel

User Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned InterruptUser Assigned Interrupt—Lowest Priority

NA01234567101112131415

NA0x00 00000x00 00200x00 00400x00 00600x00 00800x00 00A00x00 00C00x00 00E00x00 01000x00 01200x00 01400x00 01600x00 01800x00 01A00x00 01C00x00 01E0

0–345678–9101112–15Reserved

InterruptNestingEnableGlobalInterruptEnableReserved

MAC-Biased Rounding EnableReserved

PC Stack Interrupt EnableLoop Stack Interrupt EnableReserved

1These interrupt vectors start at address 0x10000 when the DSP is in

“no-boot,” run from external memory mode.

The IRPTL register is used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically main-tained during interrupt handling. To support interrupt, loop, and subroutine nesting, the PC stack is 33levels deep, the loop stack

is eight levels deep, and the status stack is 16levels deep. To prevent stack overflow, the PC stack can generate a stack-level interrupt if the PC stack falls below three locations full or rises above 28 locationsfull. The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK.ENAINT;DISINT;

Table 2.Peripheral Interrupts and Priority at Reset Interrupt

ID

Reset Priority

Slave DMA/Host Port InterfaceSPORT0 ReceiveSPORT0 TransmitSPORT1 ReceiveSPORT1 TransmitSPORT2 Receive/SPI0SPORT2 Transmit/SPI1UART ReceiveUART TransmitTimer 0Timer 1Timer 2

Programmable Flag A (any PFx)Programmable Flag B (any PFx)Memory DMA port012345671011121314012345671011111111

At reset, interrupt servicing is disabled.For quick servicing of interrupts, a secondary set of DAG and computational registers exist. Switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the DSP’s state.DMA Controller

Interrupt routines can either be nested with higher priority inter-rupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The emulation, power-down, and reset interrupts are nonmaskable with the IMASK register, but software can use the DIS INT instruction to mask the power-down interrupt.REV. 0

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The ADSP-2191M has a DMA controller that supports automated data transfers with minimal overhead for the DSP core. Cycle stealing DMA transfers can occur between the ADSP-2191M’s internal memory and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interface. DMA-capa-ble peripherals include the Host port, SPORTs, SPI ports, and UART. Each individual DMA-capable peripheral has a dedicated DMA channel. To describe each DMA sequence, the DMA con-troller uses a set of parameters—called a DMA descriptor. When successive DMA sequences are needed, these DMA descriptors can be linked or chained together, so the completion of one DMA sequence auto-initiates and starts the next sequence. DMA sequences do not contend for bus access with the DSP core; instead DMAs “steal” cycles to access memory. 元器件交易网www.cecb2b.com

ADSP-2191M

All DMA transfers use the DMA bus shown in the functional block diagram onpage1. Because all of the peripherals use the same bus, arbitration for DMA bus access is needed. The arbi-tration for DMA bus access appears in Table4.Table 4.I/O Bus Arbitration Priority DMA Bus Master

Arbitration Priority

The DSP uses HACK to indicate to the Host when to complete an access. For a read transaction, a Host can proceed and complete an access when valid data is present in the read buffer and the Host port is not busy doing a write. For a write transac-tions, a Host can complete an access when the write buffer is not full and the Host port is not busy doing a write.Two mode bits in the Host Port configuration register HPCR [7:6] define the functionality of the HACK line. HPCR6 is ini-tialized at reset based on the values driven on HACK and HACK_P pins (shown in Table5); HPCR7 is always cleared (0) at reset. HPCR [7:6] can be modified after reset by a write access to the Host port configurationregister.Table 5.Host Port Acknowledge Mode Selection Values Driven At ResetHACK_P

HACK

HPCR [7:6] Initial ValuesBit 7

Bit 6

SPORT0 Receive DMASPORT1 Receive DMASPORT2 Receive DMASPORT0 Transmit DMASPORT1 Transmit DMASPORT2 Transmit DMASPI0 Receive/Transmit DMASPI1 Receive/Transmit DMAUART Receive DMAUART Transmit DMAHost Port DMAMemory DMA

Host Port

0—Highest123456710

11—Lowest

Acknowledge Mode

The ADSP-2191M’s Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP’s memory space, boot space, or internal I/O space. Examples of Hosts include external micro-controllers, microprocessors, orASICs. The Host port is a multiplexed address and data bus that provides both an 8-bit and a 16-bit data path and operates using an asyn-chronous transmission protocol. Through this port, an off-chip Host can directly access the DSP’s entire memory space map, boot memory space, and internal I/O space. To access the DSP’s internal memory space, a Host steals one cycle per access from the DSP. A Host access to the DSP’s external memory uses the external port interface and does not stall (or steal cycles from) the DSP’s core. Because a Host can access internal I/O memory space, a Host can control any of the DSP’s I/O mapped peripherals.The Host port is most efficient when using the DSP as a slave and uses DMA to automate the incrementing of addresses for these accesses. In this case, an address does not have to be trans-ferred from the Host for every datatransfer.Host Port Acknowledge (HACK) Modes

0011010100001001Ready ModeACKMode ACKMode Ready Mode

The functional modes selected by HPCR [7:6] are as follows (assuming active high signal):•ACK Mode—Acknowledge is active on strobes; HACK goes high from the leading edge of the strobe to indicate when the access can complete. After the Host samples the HACK active, it can complete the access by removing the strobe.The Host port then removes theHACK.•Ready Mode—Ready active on strobes, goes low to insert waitstate during the access.If the Host port cannot

complete the access, it deasserts the HACK/READY line. In this case, the Host has to extend the access by keeping the strobe asserted. When the Host samples the HACK asserted, it can then proceed and complete the access by deasserting the strobe.

While in Address Cycle Control (ACC) mode and the ACK or Ready acknowledge modes, the HACK is returned active for any address cycle.Host Port Chip Selects

The Host port supports a number of modes (or protocols) for generating a HACK output for the host. The host selects ACK or Ready Modes using the HACK_P and HACK pins. The Host port also supports two modes for address control: Address Latch Enable (ALE) and Address Cycle Control (ACC) modes. The DSP auto-detects ALE versus ACC Mode from the HALE and HWR inputs.The Host port HACK signal polarity is selected (only at reset) as active high or active low, depending on the value driven on the HACK_P pin.The HACK polarity is stored into the Host port configuration register as a read only bit.There are two chip-select signals associated with the Host port: HCMS and HCIOMS. The Host Chip Memory Select (HCMS) lets the Host select the DSP and directly access the DSP’s inter-nal/external memory space or boot memory space. The Host Chip I/O Memory Select (HCIOMS) lets the Host select the DSP and directly access the DSP’s internal I/O memory space.Before starting a direct access, the Host configures Host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the IJPG register). The DSP generates the needed memory select signals during the access, based on the target address. The Host port interface combines the data from one, two, or three consecutive Host accesses (up to one 24-bit value) into a single DMA bus access to prefetch Host direct reads or to post direct writes. During assembly of larger words, the Host port interface asserts ACK for –8–

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each byte access that does not start a read or complete a write. Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully.DSP Serial Ports (SPORTs)

The ADSP-2191M incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features:•Bidirectional operation—each SPORT has independent transmit and receive pins.

•Double-buffered transmit and receive ports—each port has a data register for transferring data words to and from memory and shift registers for shifting data in and out of the data registers.

•Clocking—each transmit and receive port can either use an external serial clock (40 MHz) or generate its own, in frequencies ranging from 19Hz to 40MHz.

•Word length—each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format.

•Framing—each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync.

•Companding in hardware—each SPORT can perform A-law or µ-law companding according to ITU recommen-dation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

•DMA operations with single-cycle overhead—each

SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. Either the DSP’s core or a Host processor can link or chain sequences of DMA transfers between a SPORT and memory. The chained DMA can be dynamically allocated and updated through the DMA descriptors (DMA transfer parameters) that set up the chain.

•Interrupts—each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA.

•Multichannel capability—each SPORT supports the H.100 standard.

Serial Peripheral Interface (SPI) Ports

SCKx). Two SPI chip select input pins (SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins (SPIxSEL7–1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports provide a full duplex, synchronous serial inter-face, which supports both master and slave modes and multimaster environments. Each SPI port’s baud rate and clock phase/polarities are program-mable (see equation below for SPI clock rate calculation), and each has an integrated DMA controller, configurable to support both transmit and receive data streams. The SPI’s DMA control-ler can only service unidirectional accesses at any given time.HCLK

SPI Clock Rate=--------------------------------------2×SPIBAUD

During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.UART Port

The UART port provides a simplified UART interface to another peripheral or Host. It performs full duplex, asynchronous transfers of serial data. Options for the UART include support for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART port supports two modes ofoperation:•Programmed I/O

The DSP’s core sends or receives data by writing or reading I/O-mapped THR or RBR registers, respectively. The data is double-buffered on both transmit and receive.•DMA (direct memory access)

The DMA controller transfers both transmit and receive data. This reduces the number and frequency of inter-rupts required to transfer data to and from memory. The UART has two dedicated DMA channels. These DMA channels have lower priority than most DMA channels because of their relatively low servicerates.

The UART’s baud rate (see following equation for UART clock rate calculation), serial data format, error code generation and status, and interrupts are programmable:•Supported bit rates range from 9.5 bits to 5Mbits per second (80MHz peripheral clock).

•Supported data formats are 7- to 12-bit frames.•Transmit and receive status can be configured to generate maskable interrupts to the DSP’s core.

The timers can be used to provide a hardware-assisted autobaud detection mechanism for the UART interface.HCLK-UART Clock Rate=-----------------16×D

The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input-Slave Output, MISOx) and a clock pin (Serial Clock, Where D is the programmable divisor = 1 to 65536.REV. 0–9–

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ADSP-2191M

Programmable Flag (PFx) Pins

Idle Mode

The ADSP-2191M has 16 bidirectional, general-purpose I/O, Programmable Flag (PF15–0) pins. The PF7–0 pins are dedicated to general-purpose I/O. The PF15–8 pins serve either as general-purpose I/O pins (if the DSP is connected to an 8-bit external data bus) or serve as DATA15–8 lines (if the DSP is connected to a 16-bit external data bus). The Programmable Flag pins have special functions for clock multiplier selection and for SPI port operation. For more information, see Serial Peripheral Interface (SPI) Ports on page9 and Clock Signals on page11. Ten memory-mapped registers control operation of the Program-mable Flag pins:•Flag Direction register

Specifies the direction of each individual PFx pin as input or output.

•Flag Control and Status registers

Specify the value to drive on each individual PFx output pin. As input, software can predicate instruction execution on the value of individual PFx input pins captured in this register. One register sets bits, and one register clears bits.

•Flag Interrupt Mask registers

Enable and disable each individual PFx pin to function as an interrupt to the DSP’s core. One register sets bits to enable interrupt function, and one register clears bits to disable interrupt function. Input PFx pins function as hardware interrupts, and output PFx pins function as software interrupts—latching in the IMASK and IRPTL registers.

•Flag Interrupt Polarity register

Specifies the polarity (active high or low) for interrupt sensitivity on each individual PFx pin. •Flag Sensitivity registers

Specify whether individual PFx pins are level- or

edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are signif-icant for edge-sensitivity.

Low Power Operation

When the ADSP-2191M is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. To enter Idle mode, the DSP can execute the IDLE instruction anywhere in code. To exit Idle mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.Power-Down Core Mode

When the ADSP-2191M is in Power-Down Core mode, the DSP core clock is off, but the DSP retains the contents of the pipeline and keeps the PLL running. The peripheral bus keeps running, letting the peripherals receive data. To enter Power-Down Core mode, the DSP executes an IDLE instruction after performing the following tasks:•Enter a power-down interrupt service routine•Check for pending interrupts and I/O serviceroutines•Clear (= 0) the PDWN bit in the PLLCTL register•Clear (= 0) the STOPALL bit in the PLLCTLregister•Set (= 1) the STOPCK bit in the PLLCTL registerTo exit Power-Down Core mode, the DSP responds to an interrupt and (after two cycles of latency) resumes executing instructions with the instruction after the IDLE.Power-Down Core/Peripherals Mode

When the ADSP-2191M is in Power-Down Core/Peripherals mode, the DSP core clock and peripheral bus clock are off, but the DSP keeps the PLL running. The DSP does not retain the contents of the instruction pipeline.The peripheral bus is stopped, so the peripherals cannot receive data.To enter Power-Down Core/Peripherals mode, the DSP executes an IDLE instruction after performing the followingtasks:•Enter a power-down interrupt service routine•Check for pending interrupts and I/O serviceroutines•Clear (= 0) the PDWN bit in the PLLCTL register•Set (= 1) the STOPALL bit in the PLLCTLregisterTo exit Power-Down Core/Peripherals mode, the DSP responds to a wake-up event and (after five to six cycles of latency) resumes executing instructions with the instruction after the IDLE.Power-Down All Mode

The ADSP-2191M has four low-power options that significantly reduce the power dissipation when the device operates under standby conditions. To enter any of these modes, the DSP executes an IDLE instruction. The ADSP-2191M uses configu-ration of the PDWN, STOPCK, and STOPALL bits in the PLLCTL register to select between the low-power modes as the DSP executes the IDLE. Depending on the mode, an IDLE shuts off clocks to different parts of the DSP in the different modes. The low power modes are:•Idle

•Power-Down Core

•Power-Down Core/Peripherals•Power-Down All

When the ADSP-2191M is in Power-Down All mode, the DSP core clock, the peripheral clock, and the PLL are all stopped. The DSP does not retain the contents of the instruction pipeline. The peripheral bus is stopped, so the peripherals cannot receive data.To enter Power-Down All mode, the DSP executes an IDLE instruction after performing the following tasks:•Enter a power-down interrupt service routine•Check for pending interrupts and I/O serviceroutines•Set (= 1) the PDWN bit in the PLLCTL register

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To exit Power-Down Core/Peripherals mode, the DSP responds to an interrupt and (after 500 cycles to restabilize the PLL) resumes executing instructions with the instruction after the IDLE.Clock Signals

1M⍀25MHzCLKINMSEL0(PF0)XTALCLKOUTThe ADSP-2191M can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. If a crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors and a 1M Ω shunt resistor connected as shown in Figure3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental fre-quency, microprocessor-grade crystal should be used for this configuration.If a buffered, shaped clock is used, this external clock connects to the DSP’s CLKIN pin. CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation. When an external clock is used, the XTAL input must be left unconnected.The DSP provides a user-programmable 1؋ to 32؋ multiplica-tion of the input clock, including some fractional values, to support 128 external to internal (DSP core) clock ratios. The MSEL6–0, BYPASS, and DF pins decide the PLL multiplication factor at reset. At runtime, the multiplication factor can be con-trolled in software. The combination of pullup and pull-down resistors in Figure sets up a core clock ratio of6:1, which produces a 150MHz core clock from the 25MHz input. For other clock multiplier settings, see the ADSP-219x/2191 DSP Hardware Reference.The peripheral clock is supplied to the CLKOUT pin. All on-chip peripherals for the ADSP-2191M operate at the rate set by the peripheral clock. The peripheral clock is either equal to the core clock rate or one-half the DSP core clock rate. This selection is controlled by the IOSEL bit in the PLLCTL register. The maximum core clock is160MHz and the maximum periph-eral clock is80MHz—the combination of the input clock and core/peripheral clock ratios may not exceed these limits.Reset

VDDADSP-2191MVDDMSEL1(PF1)MSEL2(PF2)RUNTIMEPFPINI/OMSEL3(PF3)MSEL4(PF4)MSEL5(PF5)THEPULL-UP/PULL-DOWNRESISTORSONTHEMSEL,DF,ANDBYPASSPINSSELECTTHECORECLOCKRATIO.HERE,THESELECTION(6:1)AND25MHzINPUTCLOCKPRODUCEA150MHzCORECLOCK.MSEL6(PF6)DF(PF7)BYPASSRESETSOURCERESETFigure 3.External Crystal Connections

The RESET input contains some hysteresis. If using an RC circuit to generate your RESET signal, the circuit should use an external Schmidt trigger.The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. Program control jumps to the location of the on-chip boot ROM (0xFF0000).Power Supplies

The RESET signal initiates a master reset of the ADSP-2191M. The RESET signal must be asserted during the powerup sequence to assure proper initialization. RESET during initial powerup must be held long enough to allow the internal clock to stabilize. The powerup sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 100µs ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this powerup sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specifica- tion,tWRST. The ADSP-2191M has separate power supply connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 2.5V requirement. The external supply must be connected to a 3.3V supply. All external supply pins must be connected to the same supply.Powerup Sequence

Power up together the two supplies VDDEXT and VDDINT. If they cannot be powered up together, power up the internal (core) supply first (powering up the core supply first reduces the risk of latchup events.Booting Modes

The ADSP-2191M has five mechanisms (listed in Table6) for automatically loading internal program memory afterreset. Two No-boot modes are also supported.REV. 0–11–

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Table 6.Select Boot Mode (OPMODE, BMODE1, and BMODE0) OPMODEBMODE1BMODE0•Execute from memory external 8 bits (No Boot)—

Execution starts from Page1 of external memory space, packing either 8- or 16-bit external data into 24-bit internal data. The External Port Interface is config-ured for the default clock multiplier (128) and read waitstates (7).

•Boot from UART—The Host downloads

boot-stream-formatted program using an autobaud handshake sequence. The Host agent selects a baud rate within the UART’s clocking capabilities. After a hardware reset, the DSP’s UART expects a 0xAA character (eight bits data, one start bit, one stop bit, no parity bit) on the RXD pin to determine the bit rate; and then replies with an OK string. Once the host receives this OK it downloads the boot stream without further handshake.The UART boot routine is located in internal ROM memory space and uses the top 16 locations of Page0 program memory and the top 272 locations of Page0 data memory.•Boot from SPI, up to 4K bits—The SPI0 port uses the SPI0SEL1 (reconfigured PF2) output pin to select a single serial EEPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EEPROMs of ≤4K bit (12-bit address range). The SPI0 boot routine located in internal ROM memory space executes a boot-stream-formatted program, using the top 16 locations of Page0 program memory and the top 272 locations of Page0 data memory. The SPI boot configu-ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1, 8-bit data, and MSB first.

•Boot from SPI, from >4K bits to 512K bits—The SPI0 port uses the SPI0SEL1 (re-configured PF2) output pin to select a single serial EEPROM device, submits a read command at address 0x00, and begins clocking consecu-tive data into internal or external memory. Use only SPI-compatible EEPROMs of ≥4K bit (16-bit address range). The SPI0 boot routine, located in internal ROM memory space, executes a boot-stream-formatted

program, using the top 16 locations of Page0 program memory and the top 272 locations of Page0 data memory.As indicated in Table6, the OPMODE pin has a dual role, acting as a boot mode select during reset and determining SPORT or SPI operation at runtime. If the OPMODE pin at reset is the opposite of what is needed in an application during runtime, the application needs to set the OPMODE bit appropriately during runtime prior to using the corresponding peripheral.Bus Request and Bus Grant

Function

00001111

00110011

01010101

Execute from external memory 16bits (NoBoot)

Boot from EPROMBoot from HostReserved

Execute from external memory 8bits (No Boot)

Boot from UART

Boot from SPI, up to 4KbitsBoot from SPI, >4Kbits up to 512Kbits

The OPMODE, BMODE1, and BMODE0 pins, sampled during hardware reset, and three bits in the Reset Configuration Register implement these modes:•Execute from memory external 16 bits—The memory boot routine located in boot ROM memory space executes a boot-stream-formatted program located at address 0x010000 of boot memory space, packing 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (128) and read waitstates (7).

•Boot from EPROM—The EPROM boot routine located in boot ROM memory space fetches a boot-stream-for-matted program located at physical address 0x00 0000 of boot memory space, packing 8- or 16-bit external data into 24-bit internal data. The External Port Interface is configured for the default clock multiplier (32) and read waitstates (7).

•Boot from Host—The (8- or 16-bit) Host downloads a boot-stream-formatted program to internal or external memory. The Host’s boot routine is located in internal ROM memory space and uses the top 16 locations of Page0 program memory and the top 272 locations of Page0 data memory.

The internal boot ROM sets semaphore A (an IO register within the Host port) and then polls until the semaphore is reset. Once detected, the internal boot ROM will remap the interrupt vector table to Page0 internal memory and jump to address 0x00 0000 internal memory. From the point of view of the host interface, an external host has full control of the DSP's memory map. The Host has the freedom to directly write internal memory, external memory, and internal I/O memory space. The DSP core execution is held off until the Host clears the semaphore register. This strategy allows the maximum flexibility for the Host to boot in the program and data code, by leaving it up to theprogrammer.

The ADSP-2191M can relinquish control of the data and address buses to an external device. When the external device requires access to the bus, it asserts the bus request (BR) signal. The (BR) signal is arbitrated with core and peripheral requests. External Bus requests have the lowest priority. If no other internal request is pending, the external bus request will be granted. Because of –12–REV. 0

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synchronizer and arbitration delays, bus grants will be provided with a minimum of three peripheral clock delays. ADSP-2191M DSPs will respond to the bus grant by:•Three-stating the data and address buses and the MS3–0, BMS, IOMS, RD, and WR output drivers.•Asserting the bus grant (BG) signal.

The ADSP-2191M will halt program execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general-purpose or periph-eral memory spaces. If an instruction requires two external memory read accesses, bus requests will not be granted between the two accesses. If an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. The external memory interface can be configured so that the core will have exclusive use of the interface. DMA and Bus Requests will be granted. When the external device releases BR, the DSP releases BG and continues program execution from the point at which it stopped.The bus request feature operates at all times, even while the DSP is booting and RESET is active.The ADSP-2191M asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems.Instruction Set Description

Development Tools

The ADSP-2191M is supported with a complete set of software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other ADSP-219x DSPs, also fully emulates the ADSP-2191M.The VisualDSP++ project management environment lets pro-grammers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathemat-ical functions. Two key points for these tools are:•Compiled ADSP-219x C/C++ code efficiency—the compiler has been developed for efficient translation of C/C++ code to ADSP-219x assembly. The DSP has architectural features that improve the efficiency of compiledC/C++code.

•ADSP-218x family code compatibility—The assembler has legacy features to ease the conversion of existing ADSP-218x applications to the ADSP-219x.

Debugging both C/C++ and assembly programs with the Visu-alDSP++ debugger, programmers can:•View mixed C/C++ and assembly code (interleaved source and object information)•Insert break points

•Set conditional breakpoints on registers, memory, and stacks

•Trace instruction execution

•Perform linear or statistical profiling of program execution

•Fill, dump, and graphically plot the contents of memory•Source level debugging

•Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the ADSP-219x development tools, including the syntax highlighting in the Visu-alDSP++ editor. This capability permits:•Control how the development tools process inputs and generate outputs.

•Maintain a one-to-one correspondence with the tool’s command line switches.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-2191M processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonin-trusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.The ADSP-2191M assembly language instruction set has an algebraic syntax that was designed for ease of coding and read-ability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits:•ADSP-219x assembly language syntax is a superset of and source-code-compatible (except for two data registers and DAG base address registers) with ADSP-218x family syntax. It may be necessary to restructure ADSP-218x programs to accommodate the ADSP-2191M’s unified memory space and to conform to its interrupt vector map.•The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR=AX0+AY0, resembles a simple equation.

•Every instruction, but two, assembles into a single, 24-bit word that can execute in a single instruction cycle. The exceptions are two dual word instructions. One writes 16- or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24-bit address specified in the instruction.

•Multifunction instructions allow parallel execution of an arithmetic, MAC, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle.

•Program flow instructions support a wider variety of con-ditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions.REV. 0

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In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.Designing an Emulator-Compatible DSP Board (Target)

As can be seen in Figure4, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing.When the emulator is not connected to this header, place jumpers across BTMS, BTCK, BTRST, and BTDI as shown in Figure5. This holds the JTAG signals in the correct state to allow the DSP to run free. Remove all the jumpers when connecting the emulator to the JTAG header.The White Mountain DSP (Product Line of Analog Devices, Inc.) family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.To use these emulators, the target’s design must include the interface between an Analog Devices JTAG DSP and the emulation header on a custom DSP target board.Target Board Header

GND12EMU3KEY(NOPIN)5BTMS7BTCKBTRST9911BTDI1346GNDTMS8TCK10TRST12TDI14The emulator interface to an Analog Devices JTAG DSP is a 14-pin header, as shown in Figure4. The customer must supply this header on the target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025\" square post header, set on 0.1\"؋0.1\" spacing, with a minimum post length of 0.235\". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board.Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15\" and 0.10\" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector.GNDTDOTOPVIEWFigure 5.JTAG Target Board Connector with No Local

Boundary ScanJTAG Emulator Pod Connector

1GND3KEY(NOPIN)5BTMS7BTCK9BTRST11BTDI13GND92EMUFigure6 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure7 displays the keep-out area for a target board header. The keep-out area allows the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.25\" square post pin.4GND6TMS8TCK10TRST12TDI14TDO0.\"

TOPVIEW0.88\"

0.24\"

Figure 4.JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in Place)

Figure 6.JTAG Pod Connector Dimensions

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Additional Information

0.10\"0.15\"This data sheet provides a general overview of the ADSP-2191M architecture and functionality. For detailed information on the core architecture of the ADSP-219x family, refer to the ADSP-219x/2191 DSP Hardware Reference. For details on the instruction set, refer to the ADSP-219x Instruction Set Reference.PIN FUNCTION DESCRIPTIONS

Figure 7.JTAG Pod Connector Keep-Out AreaDesign-for-Emulation Circuit Information

For details on target board design issues including: single processor connections, multiprocessor scan chains, signal buff-ering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.ADSP-2191M pin definitions are listed in Table7. All ADSP-2191M inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for ADDR21–0, DATA15–0, PF7-0, and inputs that have internal pull-up or pull-down resistors (TRST, BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, and RESET)—these pins can be left floating. These pins have a logic-level hold circuit that prevents input from floating internally. The following symbols appear in the Type column of Table: G = Ground, I=Input, O = Output, P=Power Supply, and T = Three-State.Table 7.Pin Function Descriptions Pin Type

Function

A21–0D7–0D15 /PF15

/SPI1SEL7D14 /PF14

/SPI0SEL7D13 /PF12

/SPI1SEL6D12 /PF12

/SPI0SEL6D11 /PF11

/SPI1SEL5D10 /PF10

/SPI0SEL5D9 /PF9

/SPI1SEL4D8 /PF8

/SPI0SEL4PF7

/SPI1SEL3 /DFPF6

/SPI0SEL3 /MSEL6O/TI/O/TI/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TI/OI

I/O/TII

I/O/TII

External Port Address Bus

External Port Data Bus, least significant 8 bits

Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave Select output 7 (if 8-bit external bus, when SPI1 enabled)

Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave Select output 7 (if 8-bit external bus, when SPI0 enabled)

Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave Select output 6 (if 8-bit external bus, when SPI1 enabled)

Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave Select output 6 (if 8-bit external bus, when SPI0 enabled)

Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave Select output 5 (if 8-bit external bus, when SPI1 enabled)

Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave Select output 5 (if 8-bit external bus, when SPI0 enabled)

Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select output 4 (if 8-bit external bus, when SPI1 enabled)

Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select output 4 (if 8-bit external bus, when SPI0 enabled)

Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency (divisor select for PLL input during boot)

Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6 (during boot)

REV. 0–15–

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ADSP-2191M

Table 7.Pin Function Descriptions (continued)Pin Type

Function

PF5 /SPI1SEL2 /MSEL5PF4

/SPI0SEL2 /MSEL4PF3

/SPI1SEL1 /MSEL3PF2

/SPI0SEL1 /MSEL2PF1

/SPISS1 /MSEL1PF0

/SPISS0 /MSEL0RDWRACKBMSIOMSMS3–0BRBGBGH

HAD15–0HA16HACK_PHRDHWRHACKHALEHCMSHCIOMSCLKINXTAL

BMODE1–0OPMODECLKOUTBYPASSRCLK1–0RCLK2/SCK1RFS1–0

RFS2/MOSI1TCLK1–0TCLK2/SCK0TFS1–0

TFS2/MOSI0DR1–0

DR2/MISO1DT1–0

DT2/MISO0TMR2–0I/O/TII

I/O/TII

I/O/TII

I/O/TII

I/O/TII

I/O/TIIO/TO/TIO/TO/TO/TIOOI/O/TIIIIOIIIIOIIOI

I/O/TI/O/TI/O/TI/O/TI/O/TI/O/TI/O/TI/O/TI/TI/O/TO/TI/O/TI/O/T

Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 (during boot)

Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 (during boot)

Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3 (during boot)

Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2 (during boot)

Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1 (during boot)

Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0 (during boot)

External Port Read StrobeExternal Port Write Strobe

External Port Access Ready AcknowledgeExternal Port Boot Space SelectExternal Port IO Space Select

External Port Memory Space SelectsExternal Port Bus RequestExternalPortBusGrant

External Port Bus Grant Hang

Host Port Multiplexed Address and Data BusHost Port MSB of Address BusHost Port ACK PolarityHost Port Read StrobeHost Port Write Strobe

Host Port Access Ready Acknowledge

Host Port Address Latch Strobe or Address Cycle Control

Host Port Internal Memory–Internal I/O Memory–Boot Memory SelectHost Port Internal I/O Memory SelectClock Input/Oscillator inputOscillator output

Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85kΩ internal pull-up resistors.Operating Mode. The OPMODE pin has a 85kΩ internal pull-up resistor.Clock Output

Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85kΩ internal pull-up resistor.SPORT1–0 Receive Clock

SPORT2 Receive Clock/SPI1 Serial ClockSPORT1–0 Receive Frame Sync

SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input dataSPORT1–0 Transmit Clock

SPORT2 Transmit Clock/SPI0 Serial ClockSPORT1–0 Transmit Frame Sync

SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input dataSPORT1–0 Serial Data Receive

SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output dataSPORT1–0 Serial Data Transmit

SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output dataTimer output or capture

–16–

REV. 0

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ADSP-2191M

Table 7.Pin Function Descriptions (continued)Pin Type

Function

RXDTXDRESETIOI

TCKTMSTDITDOTRST

IIIOI

EMUVDDINTVDDEXTGNDNC

OPPG

UART Serial Receive DataUART Serial Transmit Data

Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at powerup. The RESET pin has an 85kΩ internal pull-up resistor.Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85kΩ internal pull-up resistor.

Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85kΩ internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a 85kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65kΩ internal pull-down resistor.

Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board connector only.

Core Power Supply. Nominally 2.5V dc and supplies the DSP’s core processor. (four pins)I/O Power Supply. Nominally 3.3V dc. (nine pins)Power Supply Return. (twelve pins)

Do Not Connect. Reserved pins that must be left open and unconnected.

REV. 0–17–

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ADSP-2191MSPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

1

Test Conditions

K Grade (Commercial)Min MaxB Grade (Industrial)Min Max

Unit

VDDINTVDDEXTVIHVILTAMB

1

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

High Level Input Voltage @ VDDINT = max,

VDDEXT = max

Low Level Input Voltage @ VDDINT = min,

VDDEXT = min

Ambient Operating Temperature

2.372.972.0–0.30

2.633.6

2.372.97

2.633.6

VV

VDDEXT+0.32.00.870

–0.3–40

VDDEXT+0.3V0.8+85

VºC

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

Parameter1

Test Conditions

K and B GradesMin Typ

Max

Unit

VOHVOLIIHIILIIHPIILPIOZHIOZLCIN

High Level Output Voltage2 Low Level Output Voltage2High Level Input Current3, 4Low Level Input Current3, 5High Level Input Current5Low Level Input Current4Three-State Leakage Current6Three-State Leakage Current6Input Capacitance7,8

@ VDDEXT = min, IOH = –0.5 mA@ VDDEXT = min, IOL = 2.0 mA@ VDDEXT = max, VIN = VDD max@ VDDEXT = max, VIN = 0 V

@ VDDEXT = max, VIN = VDD max@ VDDEXT = max, VIN = 0 V

@ VDDEXT = max, VIN = VDD max@ VDDEXT = max, VIN = 0 VfIN = 1 MHz, TCASE = 25°C,VIN = 2.5V

2.4

0.41010

3020

1007010108

VVµAµAµAµAµAµApF

1Specifications subject to change without notice.

2Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,

BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1.

3Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P.4

Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.5Applies to input pin with internal pull-down: TRST.6

Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx, HAD15–0, TMR2–0.7Applies to all signal pins.8Guaranteed, but not tested.

–18–REV. 0

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ADSP-2191M

ABSOLUTE MAXIMUM RATINGS

VDDINT Internal (Core) Supply Voltage1,2. . –0.3 V to 3.0 VVDDEXT External (I/O) Supply Voltage. . . . –0.3 V to 4.6 VVIL–VIH Input Voltage . . . . . . . . –0.5 V to VDDEXT+0.5 VVOL–VOH Output Voltage Swing. –0.5 V to VDDEXT+0.5 VTSTOREStorage Temperature Range . . . . . .–65ºC to 150ºCTLEADLead Temperature of ST-144 (5 seconds). . . .185ºC

Specifications subject to change without notice.

Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

12

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000Vreadily accumulate on the human body and test equipment and can discharge withoutdetection. Although the ADSP-2191M features proprietary ESD protection circuitry,permanent damage may occur on devices subjected to high-energy electrostaticdischarges. Therefore, proper ESD precautions are recommended to avoid perfor-mance degradation or loss of functionality.

Power Dissipation

Using the operation-versus-current information in Table8, designers can estimate the ADSP-2191M’s internal power supply (VDDINT) input current for a specific application, according to the formula for IDDINT calculation beneath Table8. For calculation of external supply current and total supply current, see Power Dissipation on page41.Table 8.Operation Types Versus Input Current

K-Grade

IDDINT(mA) CCLK = 160 MHzCore

Activity

Typ1

Max2

PeripheralTyp1

Max2

B-Grade

IDDINT(mA)1 CCLK = 140 MHzCoreTyp1

Max2

PeripheralTyp1

Max2

Power Down3Idle 14Idle 25Typical6Peak7

1Test conditions: V2

100µA11184215600µA222102400560606050µA8707070100µA11165195500µA221852100455555550µA7626262

DDINT= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.

Test conditions: VDDINT= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.3

PLL, Core, peripheral clocks, and CLKIN are disabled.4PLL is enabled and Core and peripheral clocks are disabled.5

Core CLK is disabled and peripheral clock is enabled.

6All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using a linear address sequence. 50% of the instructions are type 3 instructions.

7All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear address sequence.

IDDINT=(%Typical×IDDINT-TYPICAL)+(%Idle×IDDINT-IDLE)+(%Power Down×IDDINT-PWRDWN)

REV. 0–19–

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ADSP-2191M

TIMING SPECIFICATIONS

This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be added meaningfully to derive longer times.Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation.Timing requirements guarantee that the processor operates correctly with other devices.Clock In and Clock Out Cycle Timing

Table9 and Figure8 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.Table 9.Clock In and Clock Out Cycle TimingParameter

Min

Max

Unit

Switching CharacteristicstCKODCLKOUT Delay from CLKINtCKOCLKOUT Period1

Timing Requirements

CLKIN Period2, 3tCK

tCKLCLKIN Low PulsetCKHCLKIN High PulsetWRSTRESET Asserted Pulsewidth LowtMSSMSELx/BYPASS Stable Before RESET Deasserted Setup

MSELx/BYPASS Stable After RESET Deasserted HoldtMSH

MSELx/BYPASS Stable After RESET Asserted tMSD

Flag Output Disable Time After RESET AssertedtPFD

2In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t3In bypass mode, t

CK=tCCLK.

CK=tCCLK.

012.5104.54.5

200tCLKOUT401000

5.8

nsnsnsnsnsnsµsnsnsns

200

20010

1CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

–20–REV. 0

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ADSP-2191M

tCKCLKINtCKLtCKHtWRSTRESETtMSDtPFDMSEL6–0BYPASSDFtMSStMSHtCKODCLKOUTtCKOFigure 8. Clock In and Clock Out Cycle Timing

REV. 0–21–

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ADSP-2191M

Programmable Flags Cycle Timing

Table10 and Figure9 describe Programmable Flag operations. Table 10.Programmable Flags Cycle TimingParameter

Min

Max

Unit

Switching CharacteristicstDFOFlag Output Delay with Respect to CLKOUTtHFOFlag Output Hold After CLKOUT HighTiming Requirement

Flag Input Hold is asynchronoustHFI

3

7

6nsnsns

CLKOUTtDFOPF(OUTPUT)tHFOFLAGOUTPUTtHFIPF(INPUT)FLAGINPUTFigure 9. Programmable Flags Cycle Timing

Timer PWM_OUT Cycle Timing

Table11 and Figure10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an absolute maximum input frequency of 40MHz.Table 11.Timer PWM_OUT Cycle TimingParameter

Min

Max

Unit

Switching Characteristic

Timer Pulsewidth Output1tHTO

1The minimum time for t

HTO is one cycle, and the maximum time for tHTO equals (2

12.5

32–1) cycles.

(232–1) cycles

ns

HCLKtHTOPWM_OUTFigure 10. Timer PWM_OUT Cycle Timing

–22–REV. 0

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ADSP-2191M

External Port Write Cycle Timing

Table12 and Figure11 describe external port write operations.The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference.Table 12.External Port Write Cycle TimingParameter1, 2

Min

Max

Unit

Switching CharacteristicstCSWSChip Select Asserted to WR Asserted DelaytAWSAddress Valid to WR Setup and DelaytWSCSWR Deasserted to Chip Select DeassertedtWSAWR Deasserted to Address InvalidtWWWR Strobe Pulsewidth

WR to Data Enable Access DelaytCDA

tCDDWR to Data Disable Access DelaytDSWData Valid to WR Deasserted SetuptDHWWR Deasserted to Data Invalid Hold Time; E_WHC4tDHWWR Deasserted to Data Invalid Hold Time; E_WHC4tWWRWR Deasserted to WR, RD AssertedTiming Requirements

ACK Strobe PulsewidthtAKW

ACK Delay from WR LowtDWSAK

1t3

HCLK is the peripheral clock period.

2These are timing parameters that are based on worst-case operating conditions.

0.5tHCLK–40.5tHCLK–30.5tHCLK–40.5tHCLK–3tHCLK–2+W30.5tHCLK–3tHCLK+1+W33.4

tHCLK+3.4tHCLK12.50

0

0.5tHCLK+4tHCLK+7+W3

nsnsnsnsnsnsnsnsnsns

nsns

W = (number of waitstates specified in wait register) ؋ tHCLK.4Write hold cycle–memory select control registers (MS ؋ CTL).

tCSWSMS3–0IOMSBMStWSCSA21–0tAWSWRtWWtWSAtDWSAKACKtAKWtWWRtCDDtCDAtDSWtDHWD15–0RDFigure 11. External Port Write Cycle Timing

REV. 0–23–

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ADSP-2191M

External Port Read Cycle Timing

Table13 and Figure12 describe external port read operations. For additional information on the ACK signal, see the discussion onpage23.Table 13.External Port Read Cycle TimingParameter1, 2Min

Max

Unit

Switching CharacteristicstCSRSChip Select Asserted to RD Asserted Delay

Address Valid to RD Setup and DelaytARS

tRSCSRD Deasserted to Chip Select Deasserted SetuptRWRD Strobe PulsewidthtRSARD Deasserted to Address Invalid SetuptRWRRD Deasserted to WR, RD AssertedTiming Requirements

ACK Strobe PulsewidthtAKW

tRDARD Asserted to Data Access SetuptADAAddress Valid to Data Access SetuptSDAChip Select Asserted to Data Access SetuptSDData Valid to RD Deasserted SetuptHRDRD Deasserted to Data Invalid Hold

ACK Delay from RD LowtDRSAK

1

0.5tHCLK–3

0.5tHCLK–30.5tHCLK–2tHCLK–2+W30.5tHCLK–2tHCLKtHCLK

nsnsnsnsns

700

tHCLK–4+WtHCLK+W3tHCLK+W3

3

nsnsnsnsnsnsns

tHCLK is the peripheral clock period.

2These are timing parameters that are based on worst-case operating conditions.

3W = (number of waitstates specified in wait register) ؋ t

HCLK.

MS3–0IOMSBMStCSRStRSCSA21–0tARSRDtRWtRSAtDRSAKtAKWACKtRWRtCDAtSDtHRDD15–0tRDAtADAtSDAWRFigure 12. External Port Read Cycle Timing

–24–REV. 0

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ADSP-2191M

External Port Bus Request and Grant Cycle Timing

Table14 and Figure13 describe external port bus request and bus grant operations.Table 14.External Port Bus Request and Grant Cycle TimingParameter1, 2

Min

Max

Unit

Switching CharacteristicstSDCLKOUT High to xMS, Address, and RD/WR DisabletSECLKOUT Low to xMS, Address, and RD/WREnabletDBGCLKOUT High to BG Asserted Setup

CLKOUT High to BG Deasserted Hold TimetEBG

tDBHCLKOUT High to BGH Asserted SetuptEBHCLKOUT High to BGHDeassertedHoldTimeTiming RequirementstBSBR Asserted to CLKOUT High SetuptBHCLKOUT High to BR Deasserted Hold Time

1

0

00004.60

0.5tHCLK+144444nsnsnsnsnsnsnsns

tHCLK is the peripheral clock period.

2These are timing parameters that are based on worst-case operating conditions.

CLKOUT BRtBStBH tSDMS3–0IOMSBMStSEtSDtSEA21–0tSDWRRDtSEtDBGtEBGBGtDBHtEBHBGHFigure 13. External Port Bus Request and Grant Cycle Timing

REV. 0–25–

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ADSP-2191M

Host Port ALE Mode Write Cycle Timing

Table15 and Figure14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onpage8.Table 15.Host Port ALE Mode Write Cycle TimingParameter

Min

Max

Unit

Switching CharacteristicstWHKS1HWR Asserted to HACK Asserted (Setup, ACK Mode) First

Byte

HWR Asserted to HACK Asserted (Setup, ACK Mode)2tWHKS2

tWHKHHWR Deasserted to HACK Deasserted (Hold, ACK Mode)tWHStWHH

HWR Asserted to HACK Asserted (Setup, Ready Mode)HWR Asserted to HACK Deasserted (Hold, Ready Mode) First Byte

10

5tHCLK+tNH11010

10

5tHCLK+tNH1

nsnsnsnsns

0

Timing Requirements

HCMS or HCIOMS Asserted to HALE AssertedtCSAL

tALPWHALE Asserted PulsewidthtALCSWHALE Deasserted to HCMS or HCIOMS DeassertedtWCSWHWR Deasserted to HCMS or HCIOMS DeassertedtALWHALE Deasserted to HWR AssertedtWCSHWR Deasserted (After Last Byte) to HCMS or

HCIOMS Deasserted (Ready for Next Write)

HACK Asserted to HWR Deasserted (Hold, ACK Mode)tHKWD

tAALSAddress Valid to HALE Deasserted (Setup)tALAHHALE Deasserted to Address Invalid (Hold)tDWSData Valid to HWR Deasserted (Setup)tWDHHWR Deasserted to Data Invalid (Hold)

1

0

410101.52441

nsnsnsnsnsnsnsnsnsnsns

tNH are peripheral bus latencies (n؋tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory at the same time.

2Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

–26–REV. 0

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ADSP-2191M

HCMSHIOMStCSALHALEtALPWtALCSWtWCSWtALWHWRtWCStWHKSHACK(ACKMODE)tHKWDtWHKHHACKEACHBYTEtWHHtWHSHACK(READYMODE)HACKFIRSTBYTEtALAHtAALStDWStWDHHAD15–0HA16ADDRESSVALIDSTARTFIRSTWORDDATAVALIDFIRSTBYTEDATAVALIDLASTBYTEADDRESSVALIDSTARTNEXTWORDFigure 14. Host Port ALE Mode Write Cycle Timing

REV. 0–27–

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ADSP-2191M

Host Port ACC Mode Write Cycle Timing

Table16 and Figure15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onpage8.Table 16.Host Port ACC Mode Write Cycle TimingParameter

Min

Max

Unit

Switching CharacteristicstWHKS1HWR Asserted to HACK Asserted (ACK Mode) First Byte

HWR Asserted to HACK Asserted (Setup, ACK Mode)2tWHKS2

tWHKHHWR Deasserted to HACK Deasserted (Hold, ACK Mode)tWHSHWR Asserted to HACK Asserted (Setup, Ready Mode)tWHHHWR Asserted to HACK Deasserted (Hold, Ready Mode)

First Byte

HWR Asserted to HACK Asserted (Setup) During Address tWSHKS

Latch

HWR Deasserted to HACK Deasserted (Hold) During tWHHKH

Address LatchTiming Requirements

HWR Asserted to HALE Deasserted (Delay)tWAL

tCSALHCMS or HCIOMS Asserted to HALE Asserted (Delay)tALCSHALE Deasserted to Optional HCMS or HCIOMS

Deasserted

HWR Deasserted to HCMS or HCIOMS DeassertedtWCSW

HALE Asserted to HWR AssertedtALW

tCSWHCMS or HCIOMS Asserted to HWR AssertedtWCSHWR Deasserted (After Last Byte) to HCMS or

HCIOMS Deasserted (Ready for Next Write)

tALEWHALE Deasserted to HWR Asserted

HACK Asserted to HWR Deasserted (Hold, ACK Mode)tHKWD

tADWAddress Valid to HWR Asserted (Setup)tWADHWR Deasserted to Address Invalid (Hold)tDWSData Valid to HWR Deasserted (Setup)tWDHHWR Deasserted to Data Invalid (Hold)

HACK Asserted to HWR Deasserted (Hold) During Address tHKWAL

Latch2

1t2

10

0

5tHCLK+tNH1121010

5tHCLK+tNH11010

nsnsnsnsnsnsns

1.50100.50011.533222

nsnsnsnsnsnsnsnsnsnsnsnsnsns

NH are peripheral bus latencies (n؋tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

at the same time.

Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

–28–REV. 0

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ADSP-2191M

HCMSHIOMStALCStCSALHALEtWALtWCSWtCSWtALWHWRtALEWtWCStHKWALtWSHKSHACK(ACKMODE)tHKWDtWHKStWHKHHACKEACHBYTEtWHHKHHACK(READYMODE)tWHStWHHHACKFIRSTBYTEtWADtADWHAD15–0HA16ADDRESSVALIDSTARTFIRSTWORDtDWSDATAVALIDFIRSTBYTEtWDHDATAVALIDLASTBYTEADDRESSVALIDSTARTNEXTWORDFigure 15. Host Port ACC Mode Write Cycle Timing

REV. 0–29–

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ADSP-2191M

Host Port ALE Mode Read Cycle Timing

Table17 and Figure16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onpage8.Table 17.Host Port ALE Mode Read Cycle TimingParameter

Min

Max

Unit

Switching CharacteristicstRHKS1HRD Asserted to HACK Asserted (ACK Mode) First Byte

HRD Asserted to HACK Asserted (Setup, ACK Mode)2tRHKS2

tRHKHHRD Deasserted to HACK Deasserted (Hold, ACK Mode)tRHSHRD Asserted to HACK Asserted (Setup, Ready Mode)tRHHHRD Asserted to HACK Deasserted (Hold, Ready Mode)

First Byte

HRD Deasserted to Data Invalid (Hold)tRDH

HRD Deasserted to Data DisabletRDD

Timing Requirements

HCMS or HCIOMS Asserted to HALE Asserted (Delay)tCSAL

HALE Deasserted to Optional HCMS or HCIOMS tALCS

Deasserted

tRCSWHRD Deasserted to HCMS or HCIOMS DeassertedtALRHALE Deasserted to HRD AssertedtRCSHRD Deasserted (After Last Byte) to HCMS or

HCIOMS Deasserted (Ready for Next Read)HALE Asserted PulsewidthtALPW

tHKRDHACK Asserted to HRD Deasserted (Hold, ACK Mode)tAALSAddress Valid to HALE Deasserted (Setup)tALAHHALE Deasserted to Address Invalid (Hold)

1t

12tHCLK

12tHCLK1

15tHCLK+tNH1

121010

15tHCLK+tNH1

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

10

0105041.524

NH are peripheral bus latencies (n؋tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on

the same time.

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

–30–REV. 0

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ADSP-2191M

HCMSHIOMStCSALHALEtALCStRCSWtALPWtALRtRCSHRDtRHKSHACK(ACKMODE)tHKRDtRHKHHACKFOREACHBYTEtRHSHACK(READYMODE)tRHHHACKFIRSTBYTEtALAHtAALSHAD15–0HA16ADDRESSVALIDSTARTFIRSTWORDDATAVALIDFIRSTBYTEtRDHDATAVALIDLASTBYTEtRDDADDRESSVALIDSTARTNEXTWORDFigure 16. Host Port ALE Mode Read Cycle Timing

REV. 0–31–

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ADSP-2191M

Host Port ACC Mode Read Cycle Timing

Table18 and Figure17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onpage8.Table 18.Host Port ACC Mode Read Cycle TimingParameterMinMaxUnitSwitching CharacteristicstRHKS1HRD Asserted to HACK Asserted (ACK Mode) First ByteHRD Asserted to HACK Asserted (Setup, ACK Mode)2tRHKS2tRHKHHRD Deasserted to HACK Deasserted (Hold, ACK Mode)tRHSHRD Asserted to HACK Asserted (Setup, Ready Mode)tRHHHRD Asserted to HACK Deasserted (Hold, Ready Mode) First ByteHRD Deasserted to Data Invalid (Hold)tRDHHWR Asserted to HACK Asserted (Setup) During Address tWSHKSLatchHWR Deasserted to HACK Deasserted (Hold) During tWHHKHAddress LatchHRD Deasserted to Data DisabletRDDTiming RequirementsHCMS or HCIOMS Asserted to HALE Asserted (Delay)tCSALtALCSHALE Deasserted to Optional HCMS or HCIOMS DeassertedHRD Deasserted to HCMS or HCIOMS DeassertedtRCSWtALWHALE Asserted to HWR AssertedtALERHALE Deasserted to HWR AssertedtCSRHCMS or HCIOMS Asserted to HRD AssertedHRD Deasserted (After Last Byte) to HCMS or tRCSHCIOMS Deasserted (Ready for Next Read)HWR Deasserted to HALE Deasserted (Delay)tWALtHKRDHACK Asserted to HRD Deasserted (Hold, ACK Mode)tADWAddress Valid to HWR Deasserted (Setup)HWR Deasserted to Address Invalid (Hold)tWADtHKWALHACK Asserted to HWR Deasserted (Hold) During Address Latch2112tHCLK12tHCLK115tHCLK+tNH110101015tHCLK+tNH1nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns1010100100.51002.51.5212tNH are peripheral bus latencies (n؋tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.

2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

–32–REV. 0

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ADSP-2191M

HCMSHIOMStCSALHALEtALCStRCSWtWALtALWHWRtRCStCSRtALERHRDtHKWALtWSHKSHACK(ACKMODE)tHKRDtRHKHHACKEACHBYTEtRHKStWHHKHtRHSHACK(READYMODE)tRHHHACKFIRSTBYTEtADWHAD15–0HA16ADDRESSVALIDSTARTFIRSTWORDtWADDATAVALIDFIRSTBYTEtRDHDATAVALIDLASTBYTEtRDDADDRESSVALIDSTARTNEXTWORDFigure 17. Host Port ACC Mode Read Cycle Timing

REV. 0–33–

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ADSP-2191M

Serial Ports

Table19 and Figure18 describe SPORT transmit and receive operations, while Figure19 and Figure20 describe SPORT Frame Sync operations.Table 19.Serial Ports1, 2Parameter

Min

Max

Unit

External Clock

Timing Requirements

TFS/RFS Setup Before TCLK/RCLK3tSFSE

tHFSETFS/RFS Hold After TCLK/RCLK3tSDREReceive Data Setup Before RCLK3tHDREReceive Data Hold After RCLK3tSCLKWTCLK/RCLK WidthtSCLKTCLK/RCLK PeriodInternal Clock

Timing Requirements

TFS Setup Before TCLK4; RFS Setup Before RCLK3tSFSI

tHFSITFS/RFS Hold After TCLK/RCLK3tSDRIReceive Data Setup Before RCLK3tHDRIReceive Data Hold After RCLK3External or Internal ClockSwitching Characteristics

TFS/RFS Delay After TCLK/RCLK (Internally tDFSE

Generated FS)4

TFS/RFS Hold After TCLK/RCLK (Internally tHOFSE

Generated FS)4

External Clock

Switching Characteristics

Transmit Data Delay After TCLK4tDDTE

Transmit Data Hold After TCLK4tHDTE

Internal Clock

Switching Characteristics

Transmit Data Delay After TCLK4tDDTI

tHDTITransmit Data Hold After TCLK4tSCLKIWTCLK/RCLK WidthEnable and Three-State5Switching CharacteristicstDTENEData Enable from External TCLK4tDDTTEData Disable from External TCLK4

Data Enable from Internal TCLK4tDTENI

tDDTTIData Disable from External TCLK4External Late Frame SyncSwitching Characteristics

Data Delay from Late External TFS with MCE=1, MFD=06, 7tDDTLFSE

tDTENLFSEData Enable from Late FS or MCE=1, MFD=06, 7

1

4

41.54

0.5tHCLK–12tHCLK4325

nsnsnsnsnsns

nsnsnsns

14

3

nsns

13.4

4nsns

13.4

4

0.5tHCLK–3.5

0.5tHCLK+2.5

nsnsns

00

12.1131312nsnsnsns

10.5

3.5nsns

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.2

Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).3Referenced to sample edge.4Referenced to drive edge.5Only applies to SPORT0/1.

6MCE=1, TFS enable, and TFS valid follow t

DDTENFS and tDDTLFSE.

7If external RFSD/TFS setup to RCLK/TCLK>0.5t

LSCK, tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.

–34–REV. 0

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ADSP-2191M

DATARECEIVE-INTERNALCLOCKDRIVEEDGEtSCLKIWRCLKtDFSEtHOFSERCLKtDFSEtHOFSERFStSDRIDRtHDRIDRNOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLKORTCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE.tSDREtHDRESAMPLEEDGEDATARECEIVE-EXTERNALCLOCKDRIVEEDGEtSCLKWSAMPLEEDGEtSFSItHFSItSFSEtHFSERFSDATATRANSMIT-INTERNALCLOCKDRIVEEDGEtSCLKIWTCLKtDFSEtHOFSESAMPLEEDGEDATATRANSMIT-EXTERNALCLOCKDRIVEEDGEtSCLKWTCLKtDFSESAMPLEEDGEtSFSItHFSITFStHOFSEtSFSEtHFSETFStHDTItDDTItHDTEDTtDDTEDTNOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLKORTCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE.DRIVEEDGETCLK(EXT)TFS(\"LATE,\"EXT.)tDDTENDTDRIVEEDGETCLK(INT)TFS(\"LATE,\"INT.)TCLK/RCLKtDDTINTCLK/RCLKDRIVEEDGEtDDTTEDRIVEEDGEtDDTTIDTFigure 18. Serial PortsREV. 0–35–

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ADSP-2191M

EXTERNALRFSWITHMCE=1,MFD=0DRIVERCLKtSFSE/IRFStDTENLFSEtDDTE/ItHOSFSE/ISAMPLEDRIVEtHDTE/IDT1STBIT2NDBITtDDTLFSELATEEXTERNALTFSDRIVESAMPLEDRIVETCLKttHOSFSE/ISFSE/ITFStDTENLFSEtDDTE/ItHDTE/IDT1STBIT2NDBITtDDTLFSEFigure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5tSCLK)

EXTERNALRFSWITHMCE=1,MFD=0DRIVESAMPLEDRIVERCLKttHOFSE/ISFSE/IRFStDTENLFSEtDDTE/ItHDTE/IDT1STBIT2NDBITtDDTLFSELATEEXTERNALTFSDRIVESAMPLEDRIVETCLKttHOFSE/ISFSE/ITFStDTENLFSEtDDTE/ItHDTE/IDT1STBIT2NDBITtDDTLFSEFigure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5tHCLK)

–36–REV. 0

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ADSP-2191M

Serial Peripheral Interface (SPI) Port—Master Timing

Table20 and Figure21 describe SPI port master operations. Table 20.Serial Peripheral Interface (SPI) Port—Master TimingParameterMinMaxUnitSwitching CharacteristicstSDSCIMSPIxSEL Low to First SCLK edge (x=0 or 1)tSPICHMSerial Clock High PeriodtSPICLMSerial Clock Low PeriodSerial Clock PeriodtSPICLKtHDSMLast SCLK Edge to SPIxSEL High (x=0 or 1)tSPITDMSequential Transfer DelaytDDSPIDSCLK Edge to Data Output Valid (Data Out Delay)tHDSPIDSCLK Edge to Data Output Invalid (Data Out Hold)Timing RequirementsData Input Valid to SCLK Edge (Data Input Setup)tSSPIDtHSPIDSCLK Sampling Edge to Data Input Invalid (Data In Hold)2tHCLK–32tHCLK–32tHCLK–34tHCLK–12tHCLK–32tHCLK–2008165nsnsnsnsnsnsnsnsnsnsSPIxSEL(OUTPUT)(x=0or1)tSPICHMtSDSCIMSCLK(CPOL=0)(OUTPUT)tSPICLMtSPICLKtHDSMtSPITDMtSPICLMSCLK(CPOL=1)(OUTPUT)tSPICHMtDDSPIDMOSI(OUTPUT)MSBtHDSPIDLSBCPHA=1MISO(INPUT)tSSPIDMSBVALIDtHSPIDtSSPIDLSBVALIDtHSPIDtDDSPIDMOSI(OUTPUT)CPHA=0MISO(INPUT)MSBtHDSPIDLSBtSSPIDMSBVALIDtHSPIDLSBVALIDFigure 21. Serial Peripheral Interface (SPI) Port—Master Timing

REV. 0–37–

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ADSP-2191M

Serial Peripheral Interface (SPI) Port—Slave Timing

Table21 and Figure22 describe SPI port slave operations. Table 21.Serial Peripheral Interface (SPI) Port—Slave TimingParameter

Min

Max

Unit

Switching CharacteristicstDSOESPISS Assertion to Data Out ActivetDSDHISPISS Deassertion to Data High ImpedancetDDSPIDSCLK Edge to Data Out Valid (Data Out Delay)

SCLK Edge to Data Out Invalid (Data Out Hold)tHDSPID

Timing Requirements

tSPICHSSerial Clock High PeriodtSPICLSSerial Clock Low PeriodtSPICLKSerial Clock PeriodtHDSLast SPICLK Edge to SPISS Not Asserted

Sequential Transfer DelaytSPITDS

tSDSCISPISS Assertion to First SPICLK EdgetSSPIDData Input Valid to SCLK Edge (Data Input Setup)tHSPIDSCLK Sampling Edge to Data Input Invalid (Data In Hold)

0

000

2tHCLK2tHCLK4tHCLK2tHCLK2tHCLK+42tHCLK1.62.4

8101010nsnsnsnsnsnsnsnsnsnsnsns

SPISS(INPUT)tSPICHSSCLK(CPOL=0)(INPUT)tSPICLStSPICLKtHDStSPITDStSPICLStSDSCISCLK(CPOL=1)(INPUT)tSPICHStDSOEMISO(OUTPUT)CPHA=1MOSI(INPUT)tDDSPIDtHDSPIDMSBtDDSPIDtDSDHILSBtSSPIDMSBVALIDtHSPIDtSSPIDLSBVALIDtHSPIDtDSOEMISO(OUTPUT)CPHA=0MOSI(INPUT)tDDSPIDMSBLSBtDSDHItSSPIDMSBVALIDLSBVALIDtHSPIDFigure 22. Serial Peripheral Interface (SPI) Port—Slave Timing

–38–REV. 0

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ADSP-2191M

Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure23 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.HCLK(SAMPLECLOCK)RXDRECEIVEINTERNALUARTRECEIVEINTERRUPTDATA(5–8)STOPUARTRECEIVEBITSETBYDATASTOP;CLEAREDBYFIFOREADSTARTTXDASDATAWRITTENTOBUFFERUARTTRANSMITBITSETBYPROGRAM;CLEAREDBYWRITETOTRANSMITDATA(5–8)STOP(1–2)TRANSMITINTERNALUARTTRANSMITINTERRUPTFigure 23. UART Port—Receive and Transmit Timing

REV. 0–39–

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ADSP-2191M

JTAG Test And Emulation Port Timing

Table22 and Figure24 describe JTAG port operations. Table 22.JTAG Port TimingParameter

Min

Max

Unit

Switching CharacteristicstDTDOTDO Delay from TCK LowtDSYSSystem Outputs Delay After TCK Low1Timing Requirements

TCK PeriodtTCK

tSTAPTDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK HightHTAP

tSSYSSystem Inputs Setup Before TCK Low2tHSYSSystem Inputs Hold After TCK Low2tTRSTWTRST Pulsewidth3

2

020

8

22nsnsnsnsnsnsnsns

4445

4tTCK

1System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,

TFS0, TFS1, RFS0, RFS1, BMS.

System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, CLKIN, RESET.350MHz max.

tTCKTCKtSTAPTMSTDItHTAPtDTDOTDOtSSYSSYSTEMINPUTStHSYStDSYSSYSTEMOUTPUTSFigure 24. JTAG Port Timing

–40–REV. 0

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ADSP-2191M

Output Drive Currents

Figure25 shows typical I-V characteristics for the output drivers of the ADSP-2191M. The curves represent the current drive capability of the output drivers as a function of output voltage.6040SOURCE(VDDEXT)CURRENT–mAThe external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:• Number of output pins that switch during each cycle (O)•The maximum frequency at which they can switch (f)•Their load capacitance (C)•Their voltage swing (VDD)and is calculated by the formula below.PEXT=O×C×VDD×f

2

VDDEXT=3.65V@–40°CVDDEXT=3.3V@+25°C200–20–40–60–80INPUTCURRENT–10000.5OUTPUTCURRENTVOHVDDEXT=3.0V@+85°CVOLVDDEXT=3.0V@+85°CVDDEXT=3.3V@+25°CVDDEXT=3.65V@–40°C1.01.52.02.53.0SOURCE(VDDEXT)VOLTAGE–V3.54.0The load capacitance includes the processor’s package capaci-tance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. For example, estimate PEXT with the following assumptions:•A system with one bank of external data memory—asyn-chronous RAM (16-bit)

•One K؋16 RAM chip is used with a load of 10 pF•Maximum peripheral speed CCLK = 80 MHz, HCLK = 80 MHz

•External data memory writes occur every other cycle, a rate of 1/(4tHCLK), with 50% of the pins switching•The bus cycle time is 80MHz (tHCLK = 12.5nsec)The PEXT equation is calculated for each class of pins that can drive as shown in Table23.Figure 25.Typical Drive CurrentsPower Dissipation

Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved.Table 23.PEXT Calculation ExamplePin Type

# of Pins

% Switching

؋ C

؋ f

؋ VDD2

= PEXT

AddressMSxWRData

CLKOUT1511161500—50—10pF10pF10pF10pF10pF؋20MHz؋20MHz؋40MHz؋20MHz؋80MHz؋10.9V؋10.9V؋10.9V؋10.9V؋10.9V

= .01635W=0W

= .00436W= .01744W= .00872W

PEXT=.04687W

A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation with the following formula.PTOTAL=PEXT+PINT

Test Conditions

The DSP is tested for output enable, disable, and hold time.Output Disable Time

Where:•PEXT is from Table23

•PINT is IDDINT ؋ 2.5 V, using the calculation IDDINT listed in Power Dissipation on page41.

Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.REV. 0

Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by – V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the equation below.CL∆V

tDECAY=---------------IL

–41–

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ADSP-2191M

The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure26. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays –V from the measured output high or output low voltage. The tDECAY is calculated with test loads CL and IL, and with –V equal to 0.5V.Example System Hold Time Calculation

REFERENCESIGNALTo determine the data output hold time in a particular system, first calculate tDECAY using the equation at Output Disable Time on page41. Choose –V to be the difference between the ADSP-2191M’s output voltage and the input threshold for the device requiring the hold time. A typical –V will be 0.4V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDATRWH for the write cycle).Capacitive Loading

tMEASUREDtDISVOH(MEASURED)VOH(MEASURED)–⌬VVOL(MEASURED)VOL(MEASURED)+⌬VtENA2.0V1.0VtDECAYOUTPUTSTOPSDRIVINGOUTPUTSTARTSDRIVINGHIGH-IMPEDANCESTATE.TESTCONDITIONSCAUSETHISVOLTAGETOBEAPPROXIMATELY1.5VOutput delays and holds are based on standard capacitive loads: 50pF on all pins (see Figure30). The delay and hold specifica-tions given should be derated by a factor of 1.5ns/50pF for loads other than the nominal value of 50pF. Figure28 and Figure29 show how output rise time varies with capacitance. These figures also show graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on page41.) The graphs in these figures may not be linear outside the ranges shown.40Figure 26.Output Enable/Disable

IOLRISEANDFALLTIMES–ns(10%–90%)30RISETIMETOOUTPUTPIN+1.5V50pF2010IOH0Figure 27.Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

050100150200250LOADCAPACITANCE–pFINPUTOROUTPUTFigure 29.Typical Output Rise Time (10%-90%,

VDDEXT = Minimum at Maximum Ambient Operating Temperature) vs. Load CapacitanceEnvironmental Conditions

1.5V1.5VFigure 28.Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)Output Enable Time

The thermal characteristics in which the DSP is operating influence performance.Thermal Characteristics

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure26). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball Grid Array (mini-BGA) package. The ADSP-2191M is specified for an ambient temperature (TAMB) as calculated using the formula below.To ensure that the TAMB data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.TAMB=TCASE–PD×θCA

–42–REV. 0

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ADSP-2191M

Where:30•TAMB = Ambient temperature (measured near top surface of package)

•PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation).•θCA = Value from Table24.

•For the LQFP package: θJC = 0.96°C/WFor the mini-BGA package: θJC = 8.4°C/W

OUTPUTDELAYORHOLD–ns20100Table 24.θCA Values

050100150LOADCAPACITANCE–pF200250–10Figure 30.Typical Output Delay or Hold vs. Load

Capacitance (at Maximum Case Temperature)

Airflow

(Linear Ft./Min.)Airflow

(Meters/Second)LQFP:

θCA (°C/W)Mini-BGA:θCA (°C/W)

0044.326

1000.541.424

200138.522

400235.320.9

600332.119.8

REV. 0–43–

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ADSP-2191M

144-Lead LQFP Pinout

Table25 lists the LQFP pinout by signal name. Table26 lists the LQFP pinout by pin.Table 25.144-Lead LQFP Pins (Alphabetically by Signal) Signal

Pin

No.Signal

Pin

No.Signal

Pin

No.Signal

Pin

No.Signal

Pin No.

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21ACKBGBGH

BMODE0BMODE1BMSBR84858687819293959697991011021031041061071081091201111107071113112BYPASSCLKINCLKOUTD0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15DR0DR1DR2DT0DT1DT2EMUGNDGNDGND7213213012312412512612813513613713813914014114214412606749568151629GNDGNDGNDGNDGNDGNDGNDGNDGNDHA16HACKHACK_PHAD0HAD1HAD2HAD3HAD4HAD5HAD6HAD7HAD8HAD9HAD10HAD11HAD12HAD13HAD14HAD15HALE33545577809410512913423262434671011121415171820212230HCMSHCIOMSHRDHWRIOMSMS0MS1MS2MS3

OPMODEPF0PF1PF2PF3PF4PF5PF6PF7RCLK0RCLK1RCLK2RDRESETRFS0RFS1RFS2RXDTCKTCLK02728313211411511611711983343536373839414261685012273626951527857

TCLK1TCLK2TDITDOTFS0TFS1TFS2TMR0TMR1TMR2TMSTRSTTXDVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDINTVDDINTVDDINTVDDINTWRXTAL6547757459684344457679531325406390100118131143195882127121133

–44–REV. 0

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ADSP-2191M

Table 26.144-Lead LQFP Pins (Numerically by Pin Number) Pin

No.Signal

Pin

No.Signal

Pin

No.Signal

Pin

No.Signal

Pin

No.Signal

12345671011121314151617181920212223242526272829D14D15HAD0HAD1GNDHAD2HAD3HAD4HAD5HAD6HAD7HAD8VDDEXTHAD9HAD10GNDHAD11HAD12VDDINTHAD13HAD14HAD15HA16HACK_PVDDEXTHACKHCMSHCIOMSGND30313233343536373839404142434445474849505152535455565758

HALEHRDHWRGNDPF0PF1PF2PF3PF4PF5VDDEXTPF6PF7TMR0TMR1TMR2DT2TCLK2TFS2DR2RCLK2RFS2RXDTXDGNDGNDDT0TCLK0VDDINT

59606162636566676869707172737475767778798081828384858687TFS0DR0RCLK0RFS0VDDEXTDT1TCLK1TFS1DR1RCLK1RFS1

BMODE0BMODE1BYPASSRESETTDOTDITMSGNDTCKTRSTGNDEMUVDDINTOPMODEA0A1A2A3809192939495969799100101102103104105106107108109110111112113114115116A4A5

VDDEXTA6A7A8GNDA9A10A11A12A13

VDDEXTA14A15A16A17GNDA18A19A20A21BGHBGBRBMSIOMSMS0MS1

117118119120121122123124125126127128129130131132133134135136137138139140141142143144MS2VDDEXTMS3ACKWRRDD0D1D2D3

VDDINTD4GND

CLKOUTVDDEXTCLKINXTALGNDD5D6D7D8D9D10D11D12VDDEXTD13

REV. 0–45–

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ADSP-2191M

144-Lead Mini-BGA Pinout

Table27 lists the mini-BGA pinout by signal name. Table28 lists the mini-BGA pinout by ball number. Table 27.144-Lead Mini-BGA Pins (Alphabetically by Signal)Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

Signal

Ball No.

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21ACKBGBGH

BMODE0BMODE1BMSBRJ11H9H10G12H11G10F12G11F10F11E12E11E10E9D11D10D12C11C12B12B11A11A8C10B10L10L9A10B9BYPASSCLKINCLKOUTD0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15DR0DR1DR2DT0DT1DT2EMUGNDGNDGNDM11A5C6D7A7C7A6B7A4C5B5D5A3C4B4C3A2B1B2L7K9L5H6L8H4J10A1A12E7GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDHACKHACK_PHAD0HAD1HAD2HAD3HAD4HAD5HAD6HAD7HAD8HAD9HAD10HAD11HAD12HAD13HAD14HAD15HA16F7F8F9G4G5G6H5L6M1M12H3G1C1B3C2D1D4D3D2E1E4E2F1E3F2G2F3G3H2HALEHCIOMSHCMSHRDHWRIOMSMS0MS1MS2MS3

OPMODEPF0PF1PF2PF3PF4PF5PF6PF7RCLK0RCLK1RCLK2RDRESETRFS0RFS1RFS2RXDTCKJ1J3H1J2K2E8D9A9C9D8H12K1L1M2L2M3L3K3M4K7J9J5B8L12K8M10M6K6K11

TCLK0TCLK1TCLK2TDITDOTFS0TFS1TFS2TMR0TMR1TMR2TMSTRSTTXDVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDEXTVDDINTVDDINTVDDINTVDDINTWRXTALJ6M9K5K12L11M8J8M5K4L4J4K10J12M7E5E6F5F6G7G8H7H8D6F4G9J7C8B6

–46–REV. 0

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ADSP-2191M

Table 28.144-Lead Mini-BGA Pins (Numerically by Ball Number)Ball No.

Signal

Ball No.

Signal

Ball No.Signal

Ball

No.Signal

Ball

No.

Signal

A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5GNDD13D9D5

CLKIND3D1ACKMS1BMSA21GNDD14D15HAD1D11D7XTALD4RDBRBGHA20A19HAD0HAD2D12D10D6C6C7C8C9C10C11C12D1D2D3D4D5D6D7D8D9D10D11D12E1E2E3E4E5E6E7E8E9E10CLKOUTD2WRMS2BGA17A18HAD3HAD6HAD5HAD4D8

VDDINTD0MS3MS0A15A14A16HAD7HAD9HAD11HAD8VDDEXTVDDEXTGNDIOMSA13A12E11E12F1F2F3F4F5F6F7F8F9F10F11F12G1G2G3G4G5G6G7G8G9G10G11G12H1H2H3A11A10HAD10HAD12HAD14VDDINTVDDEXTVDDEXTGNDGNDGNDA8A9A6

HACK_PHAD13HAD15GNDGNDGNDVDDEXTVDDEXTVDDINTA5A7A3HCMSHA16HACKH4H5H6H7H8H9H10H11H12J1J2J3J4J5J6J7J8J9J10J11J12K1K2K3K4K5K6K7K8DT2GNDDT0VDDEXTVDDEXTA1A2A4

OPMODEHALEHRD

HCIOMSTMR2RCLK2TCLK0VDDINTTFS1RCLK1EMUA0TRSTPF0HWRPF6TMR0TCLK2RXDRCLK0RFS0

K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12DR1TMSTCKTDIPF1PF3PF5TMR1DR2GNDDR0DT1

BMODE1BMODE0TDORESETGNDPF2PF4PF7TFS2RFS2TXDTFS0TCLK1RFS1BYPASSGND

REV. 0–47–

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ADSP-2191M

OUTLINE DIMENSIONS

144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)

22.00BSCSQ0.7520.00BSCSQ0.600.4514410911080.270.22TYP0.17SEATINGPLANE0.08MAXLEADCOPLANARITY0.151.450.051.4036731.3537721.60MAX0.50BSCDETAILALEADPITCHDETAILATOPVIEW(PINSDOWN)NOTES:1.DIMENSIONSINMILLIMETERS.2.ACTUALPOSITIONOFEACHLEADISWITHIN0.08OFITSIDEALPOSITION,WHENMEASUREDINTHELATERALDIRECTION.3.CENTERDIMENSIONSARENOMINAL.144-BALL MINI-BGA (CA-144A)

10.10A1CORNERINDEXTRIANGLE10.00SQ9.90121110987654321AB8.80CBSCDSQEF0.80GBSCHBALLJPITCHKLMTOPVIEWBOTTOMVIEW1.70DETAILAMAX0.85MIN0.25MINNOTES:1.DIMENSIONSINMILLIMETERS.0.55SEATING2.ACTUALPOSITIONOFTHEBALLGRIDIS0.50PLANEWITHIN0.15OFITSIDEALPOSITION,RELATIVETO0.45BALLDIAMETER0.10MAXBALLTHEPACKAGEEDGES.COPLANARITY3.ACTUALPOSITIONOFEACHBALLISWITHIN0.08DETAILAOFITSIDEALPOSITION,RELATIVETOTHEBALLGRID.4.CENTERDIMENSIONSARENOMINAL.–48–REV. 0

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ADSP-2191M

ORDERING GUIDE

Instruction Rate (MHz)

Package Description

Part Number

1, 2

Ambient Temperature RangeOperating Voltage

ADSP-2191MKST-1600ºC to 70ºCADSP-2191MBST-140–40ºC to +85ºCADSP-2191MKCA-1600ºC to 70ºCADSP-2191MBCA-140

–40ºC to +85ºC1ST = Plastic Thin Quad Flatpack (LQFP).

2CA = Mini Ball Grid Array

REV. 0160144-Lead LQFP2.5 Int./3.3 Ext.V140144-Lead LQFP2.5 Int./3.3 Ext.V160144-Ball Mini-BGA2.5 Int./3.3 Ext.V140144-Ball Mini-BGA2.5 Int./3.3 Ext.V

–49–

–50–REV. 0

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ADSP-2191M

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REV. 0ADSP-2191M

–51–

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PRINTED IN U.S.A.

ADSP-2191MC02936-0-4/02(0)

–52–REV. 0